SI5338C-A-GM - I2C Clock Generator, 200MHz, 4-Output | Skyworks
部品番号: SI5338C-A-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $7.45 | $7.45 |
| 10 | $6.82 | $68.20 |
| 100 | $5.97 | $597.00 |
| 500 | $5.31 | $2,655.00 |
| 1,000 | $4.65 | $4,650.00 |
SI5338C-A-GM 概要
A clock generator (or frequency synthesizer) is a timing IC that produces one or more precise reference frequencies derived from a single input reference, typically a low-cost crystal or crystal oscillator. It belongs to the broader category of clock and timing ICs, which also includes buffers, multiplexers, jitter cleaners, and phase-locked loops (PLLs). In modern digital systems, clock generators sit at the top of the timing tree and feed downstream PHYs, SoCs, FPGAs, and memory controllers, so their jitter and frequency accuracy directly bound the performance of the entire board.
Key features include any-frequency synthesis from 0.16 MHz to 200 MHz on each output, sub-200 fs RMS typical phase jitter (12 kHz to 20 MHz), four differential output drivers that can also be configured as eight single-ended CMOS clocks, I2C control interface for in-circuit reconfiguration, and a field-programmable variant via the Si5338/56-PROG-EVB. Independent output voltage rails (1.8 V, 2.5 V, or 3.3 V) eliminate level shifters when driving mixed-voltage logic.
Architecturally, the Si5338C-A-GM integrates a low-noise integer-N PLL plus four independent MultiSynth fractional-N divider blocks, each with its own output driver. This dual-stage design achieves the wide frequency range of fractional synthesis while keeping the jitter contribution of the dividers low. The I2C interface exposes a 364-byte configuration RAM that the host can rewrite at any time, allowing in-system frequency changes for FPGA bitstream reconfiguration or link-rate switching.
Typical applications include Ethernet switch PHY clocking (10/100/1G/10G), PCI Express Gen 1/2/3 reference clocks, Fibre Channel port timing, telecom line cards, FPGA fabric and transceiver reference clocks, and any system that needs multiple independent frequencies from one crystal reference. The 24-QFN (4x4) footprint is friendly to compact router and switch designs.
When designing with this part, place the input reference crystal within 5 mm of the XIN/XOUT pins and route the output traces with controlled 50 ohm impedance. Verify the in-circuit I2C configuration script against your board's frequency plan before bringing up the system, since a wrong MultiSynth setting will appear as an output stuck at the wrong rate.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone Si5338 datasheet.
ドロップイン代替品: SI5338C-A-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5338C-A-GM （同一形状・フットプリント） — 相違点: Package, Function, Number of Outputs, Control Interface, MSL Level.
クイック比較ツール — 並列比較する代替部品を選択:
SI5338C-B-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5338C-B03798-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5338C-B05777-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5338A-B-GM
✅ ドロップイン✓ 在庫あり
$8.5 / 個
データシートを見る →SI5338A-B08801-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5338C-A-GM 仕様
| 機能 | I2C-programmable any-frequency clock generator |
| Output Frequency Range | 0.16 MHz to 200 MHz per output |
| 出力数 | 4 (differential) or 8 (single-ended) |
| 出力タイプ | Differential (LVPECL/LVDS/HCSL) or CMOS, configurable |
| Control Interface | I2C (in-circuit configurable) |
| Input Reference | External crystal or CMOS clock |
| Core Supply Voltage | 2.5 V or 3.3 V |
| Output Supply Voltage | 1.8 V, 2.5 V, or 3.3 V (independent per bank) |
| Phase Jitter (RMS) | <200 fs typical (12 kHz to 20 MHz) |
| パッケージ | 24-pin QFN (4x4 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial) |
| MSLレベル | 1 (unlimited floor life) |
| RoHS ステータス | Compliant |
| Target Applications | Ethernet, PCI Express, Fibre Channel, Telecom |
SI5338C-A-GM ピン構成
| ピン 1 | VDD — Core supply voltage (2.5V or 3.3V) |
| ピン 2 | XIN — Crystal oscillator input |
| ピン 3 | XOUT — Crystal oscillator output |
| ピン 4 | GND — Ground |
| ピン 5 | SDA — I2C serial data |
| ピン 6 | SCL — I2C serial clock |
| ピン 7 | OE — Output enable (active high) |
| ピン 8 | VDDO0 — Output supply for OUT0 (1.8V/2.5V/3.3V) |
| ピン 9 | OUT0_P — Differential output 0 positive (or CMOS0) |
| ピン 10 | OUT0_N — Differential output 0 negative (or CMOS0_N) |
| ピン 11 | OUT1_P — Differential output 1 positive (or CMOS1) |
| ピン 12 | OUT1_N — Differential output 1 negative (or CMOS1_N) |
| ピン 13 | VDDO1 — Output supply for OUT1 (1.8V/2.5V/3.3V) |
| ピン 14 | GND — Ground |
| ピン 15 | OUT2_P — Differential output 2 positive (or CMOS2) |
| ピン 16 | OUT2_N — Differential output 2 negative (or CMOS2_N) |
| ピン 17 | VDDO2 — Output supply for OUT2 (1.8V/2.5V/3.3V) |
| ピン 18 | OUT3_P — Differential output 3 positive (or CMOS3) |
| ピン 19 | OUT3_N — Differential output 3 negative (or CMOS3_N) |
| ピン 20 | VDDO3 — Output supply for OUT3 (1.8V/2.5V/3.3V) |
| ピン 21 | GND — Ground |
| ピン 22 | A0 — I2C slave address LSB |
| ピン 23 | FINC — Frequency increment control input (frequency select) |
| ピン 24 | FDEC — Frequency decrement control input (frequency select) |
主な用途
SI5338C-A-GM の用途: 6 件s: Ethernet Switch PHY Clocking, PCI Express Reference Clock Distribution, Telecom Line Card Timing, FPGA Fabric and Transceiver Reference Clocks, Fibre Channel Port Timing, Industrial Test and Measurement Equipment.
Ethernet Switch PHY Clocking
The SI5338C-A-GM is ideal for 1G/10G Ethernet switch designs that need multiple independent PHY reference clocks from a single 25 MHz crystal. Its sub-200 fs RMS phase jitter over 12 kHz to 20 MHz easily meets the IEEE 802.3an and 802.3ba reference-clock jitter masks, while the I2C interface lets the host retune output frequencies during port-rate switching between 1G and 10G. Each of the four outputs can drive a separate PHY on a QSFP+ port, eliminating four separate crystal oscillators.
おすすめ
PCI Express Reference Clock Distribution
The SI5338C-A-GM's sub-200 fs RMS phase jitter and configurable HCSL output drivers make it a strong fit for PCI Express Gen 1/2/3 endpoint and root-complex reference-clock generation. Place one SI5338C-A-GM on the motherboard to drive four PCIe slots or downstream endpoints, each output set to the required 100 MHz HCSL reference, eliminating separate 100 MHz crystal oscillators per slot. The independent output voltage rails (1.8 V, 2.5 V, or 3.3 V) accommodate mixed PCIe generations on the same board.
おすすめ
Telecom Line Card Timing
Telecom line cards require multiple precise clocks (T1/E1, SyncE, IEEE 1588) that the SI5338C-A-GM can synthesize independently on each of its four outputs from a single OCXO or crystal reference. The sub-200 fs phase jitter and the ability to reconfigure frequencies via I2C over the management interface allow dynamic rate changes between 1.544 MHz (T1) and 2.048 MHz (E1) and 125 MHz SyncE without component swaps. The 24-QFN (4x4 mm) footprint fits dense AdvancedTCA and compact PCI Serial Telecom boards.
おすすめ
FPGA Fabric and Transceiver Reference Clocks
FPGA designs that need a fabric clock, a GTX/GTH/GTY transceiver reference clock, and one or two peripheral clocks (DDR memory controller, PCIe hard IP) can generate all four from a single SI5338C-A-GM. The any-frequency synthesis on each output removes the need for multiple crystal oscillators or fixed-frequency oscillators at non-standard rates like 148.5 MHz for video. The I2C interface allows bitstream-load-time frequency reconfiguration for different FPGA personality cards sharing the same baseboard.
おすすめ
Fibre Channel Port Timing
Fibre Channel 4G/8G/16G ports require 106.25 MHz, 159.375 MHz, or 212.5 MHz reference clocks with tight jitter masks that the SI5338C-A-GM meets on each of its four outputs. The four-channel architecture fits a typical 4-port FC HBA, replacing four crystal oscillators and reducing BOM cost. The 200 MHz per-output ceiling covers 16G FC requirements when paired with an external multiplier, while the I2C bus allows rate-switching between 4G/8G FC speeds via the host driver.
おすすめ
Industrial Test and Measurement Equipment
Test and measurement platforms (oscilloscopes, logic analyzers, signal generators) often need multiple isolated sample clocks, ADC clocks, and DAC clocks on one board. The SI5338C-A-GM provides four independent low-jitter clocks from a single 25 MHz reference, ideal for synchronizing multiple ADC/DAC channels in a multi-channel data-acquisition card. The 24-QFN package and -40C to +85C industrial temperature range suit bench-instrument and rack-mount environments alike.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5338C-A-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5338C-B-GM | SI5338C-B03798-GM | SI5338C-B05777-GM | SI5338A-B-GM | SI5338A-B08801-GM |
|---|---|---|---|---|---|---|
| Package | 24-QFN (4x4 mm) | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Number of Outputs | 4 differential / 8 CMOS | 4 differential / 8 CMOS | 4 differential / 8 CMOS | 4 differential / 8 CMOS | 4 differential / 8 CMOS | 4 differential / 8 CMOS |
| Output Frequency Range | 0.16 - 200 MHz | 0.16 - 200 MHz | 0.16 - 200 MHz (factory-set plan) | 0.16 - 200 MHz (factory-set plan) | 0.16 - 200 MHz (A-revision register map) | 0.16 - 200 MHz (factory-set plan) |
| Configuration Method | I2C in-circuit (blank RAM) | Factory-programmed | Factory-programmed | Factory-programmed | Factory-programmed (A-rev) | Factory-programmed (A-rev) |
| Phase Jitter (RMS) | <200 fs typical | <200 fs typical | <200 fs typical | <200 fs typical | <200 fs typical | <200 fs typical |
| Revision Register Map | C-revision | C-revision | C-revision | C-revision | A-revision (legacy) | A-revision (legacy) |
| In-Circuit Reconfigurable | Yes | No (factory-set) | No (factory-set) | No (factory-set) | No (factory-set) | No (factory-set) |
主な差別化要因
- I2C in-circuit reconfigurable vs factory-programmed （vs SI5338C-B-GM)
- C-revision register map (newer than A-revision) （vs SI5338A-B-GM)
- Independent per-bank output voltage rails （vs Single-rail clock generators)
設計ノート
Place the external reference crystal within 5 mm of the XIN/XOUT pins and route both traces symmetrically with ground-shielded traces to avoid stray capacitance that pulls the crystal off-frequency. Connect the exposed pad (EP) of the 24-QFN directly to a solid ground plane with multiple thermal vias, since EP functions as the thermal and electrical ground for the silicon die. Estimated: a 0.1 uF decoupling cap within 2 mm of each VDD pin keeps core supply ripple under 10 mV.
The Si5338C-A-GM ships with its configuration RAM blank and will not produce any output until a valid configuration is loaded via I2C at power-up. Power-on without an I2C bootloader will leave all outputs tristated - design your system MCU/FPGA firmware to push the Si5338 register map within 100 ms of asserting VDD. The OE pin is active-high and must be de-asserted during configuration to avoid glitches on the output traces.
Differential output traces (OUTx_P and OUTx_N) must be routed as a 100 ohm differential pair with matched length to within 2 mm to preserve HCSL/LVDS signal integrity. Use continuous ground reference under the pairs and avoid routing across split planes. For PCIe Gen 3 reference-clock applications, keep the Si5338 within 100 mm of the PCIe endpoint to stay below the 16 dB channel loss budget at 100 MHz.
Provide independent decoupling for each VDDO bank (VDDO0, VDDO1, VDDO2, VDDO3) since the per-bank output voltage rails (1.8 V, 2.5 V, or 3.3 V) can differ. A 10 uF bulk plus 0.1 uF and 1 nF ceramic bypass within 3 mm of each VDDO pin is recommended. Estimated: the Si5338C-A-GM draws roughly 50-80 mA per active output, so size the VDDO traces for 100 mA continuous at each bank.
コンプライアンス情報
Skyworks product page lists RoHS and lead-free compliance. AEC-Q100 not applicable (consumer/industrial timing IC, not automotive grade).
