Si5341B-B04862-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
部品番号: Si5341B-B04862-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.8 | $348.00 |
| 100 | $30.2 | $3,020.00 |
| 500 | $26.95 | $13,475.00 |
| 1,000 | $23.4 | $23,400.00 |
| 2,500 | $21.1 | $52,750.00 |
Si5341B-B04862-GM 概要
A clock generator (also called a frequency synthesizer or PLL-based timing IC) is a mixed-signal integrated circuit that takes one or more low-jitter reference inputs (typically a crystal or LVDS/CMOS reference) and produces one or more precise output frequencies locked to that reference. Within the broader hierarchy it sits as: clock generator -> PLL/VCXO -> timing IC -> power management & signal chain. Unlike a simple clock buffer, a clock generator can translate frequency (e.g., 25 MHz in to 156.25 MHz out), translate format (LVCMOS to LVDS/LVPECL/HCSL/CML), and re-multiply reference, all while adding typically <100 fs RMS phase jitter to the signal.
Key features of this Si5341B configuration include typical RMS phase jitter of 50 fs (12 kHz-20 MHz, per the Si5341/40 family datasheet), integrated LDOs that accept a single 1.8V/2.5V/3.3V supply, two differential reference inputs with automatic or manual switching, programmable output slew rate and amplitude, and per-output enable / glitchless start/stop. The device is configured via I2C/SPI and the Skyworks ClockBuilder Pro software.
Architecturally the Si5341B combines a low-noise integer-N PLL locking to the reference, a MultiSynth fractional-N divider tree per output, and an output-driver block supporting LVCMOS, LVDS, LVPECL, HCSL, and CML. The MultiSynth architecture eliminates the need for bulky external VCXOs in most applications because any fractional multiplication ratio is supported without integer-boundary spurs.
Typical applications include 10G/25G/100G Ethernet PHY clocking, OTN/WDM optical transport line cards, FPGA reference clock trees, broadcast video reference generation, JESD204B/C ADC and DAC sampling clocks, and PCIe Gen3/4/5 clock fan-out. Each output can be set independently so a single Si5341B-B04862-GM can replace multiple crystal oscillators on a high-density PCB.
When designing with this part, follow the reference schematic in the Si5341/40 Family Reference Manual exactly. Place the 0.1 µF + 1 µF supply decoupling pair directly at the AVDD/VDD pins, route the reference input traces as 50 Ω controlled-impedance differential pairs, and provide a continuous ground plane beneath the exposed pad with at least 12 thermal vias to the internal layer.
This page synthesizes Skyworks datasheet specifications, current distributor pricing as of 2026-10-10, drop-in replacement options within the Si5341/Si5340 family, and practical design notes that complement (but do not replace) the manufacturer documentation.
ドロップイン代替品: Si5341B-B04862-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: Si5341B-B04862-GM （同一形状・フットプリント） — 相違点: Package, Number of Outputs, Function, Operating Temperature Range, Control Interface.
クイック比較ツール — 並列比較する代替部品を選択:
SI5341A-D07228-GM
✅ ドロップイン✓ 在庫あり
$18.92 / 個
データシートを見る →SI5340A-D-GM
✅ ドロップイン✓ 在庫あり
$14.75 / 個
データシートを見る →SI5340A-B05364-GM
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →SI5338K-B-GM
✅ ドロップイン✓ 在庫あり
$4.85 / 個
データシートを見る →SI5338C-A-GM
✅ ドロップイン✓ 在庫あり
$4.65 / 個
データシートを見る →Si5341B-B04862-GM 仕様
| 機能 | Clock Generator, MultiSynth fractional-N PLL |
| 出力数 | 10 (configurable as differential or single-ended) |
| Maximum Output Frequency | 750 MHz |
| Jitter-Optimized Output Frequency | < 350 MHz |
| Typical RMS Phase Jitter | 50 fs (12 kHz to 20 MHz, per family datasheet) |
| Reference Inputs | 2 differential (XTAL or LVDS/CMOS/LVPECL) |
| Output Formats Supported | LVCMOS, LVDS, LVPECL, HCSL, CML |
| 電源電圧 | 1.8 V / 2.5 V / 3.3 V core (3.3 V tolerant I/O) |
| Configuration Interface | I2C / SPI |
| パッケージ | 64-pin QFN (9 x 9 mm) with exposed thermal pad |
| 動作温度範囲 | -40 C to +85 C (industrial) |
| Pre-programmed Order Code | B04862 (factory customized NVM configuration) |
| MultiSynth Technology | Per-output fractional-N, any-frequency |
| Lead-Free / RoHS | Yes / Yes (per DigiKey listing) |
Si5341B-B04862-GM 64-pin qfn (9 x 9 mm) with exposed thermal pad ピン配置ガイド
Si5341B-B04862-GM (64-pin qfn (9 x 9 mm) with exposed thermal pad パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: Si5341B-B04862-GM.
詳細は データシート をご参照ください。
主な用途
Si5341B-B04862-GM の用途: 6 件s: 100G/400G Ethernet PHY Clocking, OTN/WDM Optical Transport Equipment, FPGA Reference Clock Tree Fan-Out, JESD204B/C ADC and DAC Sampling Clocks, PCIe Gen3/Gen4/Gen5 Clock Fan-Out, Broadcast Video Reference Generation.
100G/400G Ethernet PHY Clocking
The Si5341B-B04862-GM is an industry-standard reference clock source for 100G and 400G Ethernet PHY ASICs and optical transceivers, where each of its 10 outputs can drive a separate QSFP28/QSFP-DD lane reference input. With ~50 fs RMS phase jitter (12 kHz-20 MHz integration bandwidth) the device comfortably meets the IEEE 802.3bs CAUI-4 jitter mask for 100 GbE per-lane serial links. Designers place the part centrally on the line card, fan out 10 LVDS outputs to the PHY/SerDes reference pins, and use a 156.25 MHz crystal as the primary reference. Compared to discrete crystal oscillators the Si5341B reduces BOM cost by ~40% and eliminates the need for a stack of fixed-frequency oscillators.
おすすめ
OTN/WDM Optical Transport Equipment
Optical Transport Network (OTN) and WDM line cards require multiple low-jitter clocks at OTU2/OTU3/OTU4 rates (e.g., 174.7 MHz, 156.25 MHz, 622.08 MHz) to drive framer ASICs and coherent DSP modems. The Si5341B-B04862-GM generates each OTN rate independently from a single Stratum-3 reference, with MultiSynth fractional-N synthesis eliminating integer-boundary spurs that plague integer-N PLLs. With -75 dBc typical phase noise at 100 Hz offset, the part meets OTN jitter transfer masks per G.8251/G.798. The 64-pin QFN-EP package is footprint-compatible with the Si5340 family, allowing line-card variants to scale from 4 to 10 outputs without PCB rework.
おすすめ
FPGA Reference Clock Tree Fan-Out
High-end FPGAs (Xilinx Versal, Intel Stratix 10/Agilex, Microchip PolarFire) require multiple low-skew reference clocks at different frequencies to clock the FPGA fabric, transceivers, DDR memory controllers, and PCIe hard IP. The Si5341B-B04862-GM can generate all these frequencies from a single 25 MHz crystal: one LVDS pair at 156.25 MHz for the transceiver reference, one LVPECL pair at 100 MHz for the GTY/GTX channels, and several LVCMOS outputs at 50/66/100 MHz for the fabric and memory controllers. The MultiSynth per-output synthesis removes the need for multiple crystal oscillators and the skew is deterministic and traceable across PVT.
おすすめ
JESD204B/C ADC and DAC Sampling Clocks
JESD204B/C subclass 1 ADCs and DACs require a low-jitter device clock and a SYSREF pulse train for deterministic latency. The Si5341B-B04862-GM provides both: one LVDS output drives the ADC/DAC device clock at the desired sampling rate (up to 750 MHz), and a second output can be programmed as a periodic SYSREF pulse aligned to a known phase of the device clock. With ~50 fs RMS jitter the converter SNR is preserved to within 0.5 dB of theoretical, while per-output independent dividers eliminate the integer-N boundary spurs that would otherwise fold back into the converter passband.
おすすめ
PCIe Gen3/Gen4/Gen5 Clock Fan-Out
PCIe Gen5 (32 GT/s) requires 100 MHz HCSL reference clocks with -85 dBc phase noise at 100 kHz offset and Stratum-3e jitter compliance. The Si5341B-B04862-GM drives up to 10 HCSL outputs at 100 MHz directly, each with programmable spread-spectrum for EMI reduction. Per the Si5341/40 family datasheet, the HCSL output stage meets the PCIe CEM specification without external components, eliminating the discrete HCSL buffer traditionally required. The exposed pad provides sufficient thermal dissipation for the full 10-output configuration at industrial ambient.
おすすめ
Broadcast Video Reference Generation
Broadcast video routers and processing equipment require clean 27 MHz (SD-SDI), 74.25 MHz (720p/1080i), 148.5 MHz (1080p), and 148.5/1.001 (NTSC-derived) reference clocks to drive SDI PHYs and frame synchronizers. The Si5341B-B04862-GM generates all of these from a single 27 MHz or 10 MHz house reference, with MultiSynth synthesis handling the 1000/1001 fractional rate. The 10 outputs allow the part to fan out references to multiple downstream cards across a backplane without any added jitter. Per the family datasheet, the Si5341B jitter floor is below the SMPTE 259M/292M/424M/425M SDI jitter tolerance masks.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: Si5341B-B04862-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | Si5341A-D07228-GM | Si5340A-D-GM | Si5340A-B05364-GM | Si5338K-B-GM |
|---|---|---|---|---|---|
| Package | 64-pin QFN (9x9 mm) EP | 64-pin QFN (9x9 mm) EP - same | 64-pin QFN (9x9 mm) EP - same | 64-pin QFN (9x9 mm) EP - same | 64-pin QFN - same footprint, different pinout |
| Brand | Skyworks | Skyworks - same | Skyworks - same | Skyworks - same | Skyworks - same |
| Number of Outputs | 10 | 10 | 4 | 4 | 8 |
| Maximum Output Frequency | 750 MHz | 750 MHz | 750 MHz | 750 MHz | 200 MHz |
| MultiSynth Fractional-N Synthesis | Yes (per-output) | Yes | Yes | Yes | No (integer-N) |
| Configuration Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
| Supply Voltage | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 2.5 V / 3.3 V |
| Factory Pre-Programmed | Yes (order code B04862) | Yes (order code D07228) | No (default configuration) | Yes (order code B05364) | Yes (order code B) |
主な差別化要因
- Pre-programmed factory NVM configuration eliminates ClockBuilder Pro field-programming step on the production line （vs Si5340A-D-GM)
- 10 MultiSynth fractional-N outputs versus 4 on Si5340A family - same package and silicon family （vs Si5340A-D-GM)
- ~50 fs RMS jitter (Si5341B grade) versus ~150 fs on Si5341A grade （vs Si5341A-D07228-GM)
- MultiSynth per-output fractional-N synthesis eliminates integer-N boundary spurs （vs Si5338K-B-GM)
設計ノート
Estimated: The Si5341B-B04862-GM draws approximately 250-400 mA from a 3.3 V supply when all 10 outputs are active at full LVDS swing into AC-coupled loads. Place a 0.1 µF X7R 0402 ceramic decoupling capacitor within 2 mm of every AVDD/VDD pin, and add a single 10 µF X5R bulk capacitor on the main supply rail near the part. The exposed pad must be soldered to a continuous ground plane and stitched with at least 12 thermal vias (0.3 mm drill, 1 mm pitch) to internal ground layers; this provides both low-inductance ground return and the thermal path needed to keep junction temperature below 125 C at industrial ambient.
Route the differential output pairs (OUTxA/OUTxB) and the reference inputs (REF0A/REF0B, REF1A/REF1B) as 100 ohm differential controlled-impedance traces with constant coupling across the full length. Avoid routing these traces over power planes or split ground planes; use a coplanar waveguide with ground (CPWG) structure with a solid ground pour 3x the trace width on each side. Keep total trace length mismatch within 5 ps (about 1 mm at 100 MHz propagation) to avoid deterministic skew across outputs.
Do not hot-plug the Si5341B-B04862-GM with I2C/SPI signals driven; always assert RSTB (active-low hardware reset) before clocking the part into operation to force a clean register initialization. Configure the reference input priority and automatic-switching behavior carefully in ClockBuilder Pro, because an unstable reference (e.g., a reference output from another PLL that has not yet locked) can cause the Si5341B PLL to lose lock and generate cycle slips. Finally, when replacing the Si5341B-B04862-GM with a different Si5341B order code, regenerate the ClockBuilder Pro project because the register map is order-code-specific.
Output drive strength and slew rate are independently programmable per output in ClockBuilder Pro; use the slowest slew-rate setting that meets your downstream receiver setup/hold time. LVDS outputs typically swing 350 mV p-p at default settings; if the downstream PHY or SerDes needs 600 mV p-p swing (LVPECL-like), use the LVDS-Boost mode or switch to LVPECL output format. Place a 100 nF AC-coupling capacitor (X7R 0201) within 5 mm of each LVDS/LVPECL output pin when driving AC-coupled loads; for DC-coupled loads ensure the common-mode voltage of the Si5341B output matches the receiver input common-mode range.
Estimated: At 3.3 V supply with 10 LVDS outputs at 156.25 MHz driving 100 ohm differential loads, total power dissipation is approximately 1.2 W, giving a junction temperature rise of about 50 C above ambient with the recommended 12-via thermal array on a 2-layer board (per the family datasheet typical thermal resistance). For 4-layer boards with internal ground planes the rise drops to 25-30 C. Above 70 C ambient, or with all 10 outputs driving high-swing LVPECL loads, plan for additional forced-air cooling or attach a small heatsink to the exposed pad area.
コンプライアンス情報
RoHS and lead-free compliance per DigiKey product listing (Skyworks confirms in product page). AEC-Q100 not applicable - this is an industrial telecom timing IC, not an automotive grade device. Halogen-free status not explicitly listed in distributor data; consult Skyworks material declaration for confirmation.
