SI5365-C-GQR - 1.05GHz Any-Frequency Clock Multiplier | Skyworks
部品番号: SI5365-C-GQR ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $25.15 | $25.15 |
| 10 | $24.2 | $242.00 |
| 100 | $23.55 | $2,355.00 |
| 500 | $23.1 | $11,550.00 |
| 1,000 | $22.87 | $22,870.00 |
SI5365-C-GQR 概要
A clock multiplier (frequency synthesizer) is a timing IC that generates output clocks at an integer or fractional multiple of a reference input frequency. Within the timing hierarchy it sits under clock generators and PLL (phase-locked loop) devices, serving as the precision timing backbone for serial links, line cards, and backplane systems where stable, low-jitter reference clocks are critical to bit-error-rate performance.
Key features include selectable output frequencies up to 1050 MHz, digitally programmable PLL loop bandwidth from 150 kHz to 1.3 MHz via BWSEL[1:0] pins, and flexible output signaling on CML, LVDS, LVPECL, and LVCMOS levels. The four-input, five-output architecture supports redundant reference clocking and fan-out of multiplied clocks to multiple serializers or PHYs.
Technically, the DSPLL architecture replaces the analog loop filter and external VCXO of a classical PLL with a digital loop, giving deterministic bandwidth control and jitter attenuation that does not degrade across process, voltage, and temperature. This makes it well suited to SONET OC-48/OC-192, 10 Gigabit Ethernet, and Fibre Channel timing requirements.
Typical applications include optical transport network line cards, Ethernet switch and router clock trees, and Fibre Channel storage network timing, where any-frequency synthesis from 19.44 MHz or 156.25 MHz references is required.
Design consideration: note that the SI5365 is a clock multiplier without jitter attenuation of upstream references; the Si5366 family should be evaluated when reference jitter cleanup is required. Also, this device is marked not recommended for new designs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: SI5365-C-GQR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
SI5365-B-GQR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SI5365-A-GQR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SI5365-C-GQR 仕様
| Product Type | Clock Multiplier IC (DSPLL) |
| Maximum Output Frequency | 1.05 GHz |
| Input Frequency Range | 19.44 MHz to 707.35 MHz |
| Output Frequency Range | 19.44 MHz to 1050 MHz |
| Number of Clock Inputs | 4 |
| Number of Clock Outputs | 5 |
| Number of Circuits | 1 |
| Input:Output Ratio | 4:5 |
| Output Signal Types | CML, LVDS, LVPECL, LVCMOS |
| PLL | Yes (3rd-generation DSPLL) |
| PLL Loop Bandwidth | 150 kHz to 1.3 MHz (programmable via BWSEL[1:0]) |
| External VCXO Required | No (integrated) |
| パッケージ | 100-TQFP |
| 実装タイプ | Surface Mount (SMD/SMT) |
| Packaging | Tape & Reel (TR), standard qty 250 |
| ライフサイクル状態 | Not recommended for new designs (alternatives: Si533x family) |
| Target Applications | SONET OC-48/OC-192, Ethernet, Fibre Channel |
SI5365-C-GQR 100-tqfp ピン配置ガイド
SI5365-C-GQR (100-tqfp パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: SI5365-C-GQR.
詳細は データシート をご参照ください。
主な用途
SI5365-C-GQR の用途: 6 件s: SONET OC-48/OC-192 Timing, 10 Gigabit Ethernet Switching, Fibre Channel Storage Networks, Optical Transport Network (OTN) Line Cards, High-Speed Backplane Clock Distribution, Test and Measurement Instruments.
SONET OC-48/OC-192 Timing
The SI5365-C-GQR is purpose-built for SONET OC-48 and OC-192 timing cards, where line-rate reference clocks such as 622.08 MHz and 644.53 MHz must be synthesized from standard 19.44 MHz or 155.52 MHz references. Its 19.44 MHz to 707.35 MHz input range and 1050 MHz maximum output directly cover these frequencies, and the 3rd-generation DSPLL with digitally programmable 150 kHz to 1.3 MHz loop bandwidth delivers deterministic low-jitter multiplication without external VCXO or loop filter parts. Because it multiplies without attenuating reference jitter, it is best used behind an already-clean reference or a jitter-cleaning Si5366 stage in the timing path.
おすすめ
10 Gigabit Ethernet Switching
In 10GbE switch and router line cards, MAC and PHY devices need multiple 156.25 MHz reference clocks derived from a single low-cost oscillator. The SI5365-C-GQR multiplies a 156.25 MHz or 25 MHz input to outputs up to 1050 MHz and fans out five outputs in CML, LVDS, LVPECL, or LVCMOS levels, matching different PHY input requirements from one IC. The four selectable input references also support redundant clock sources with hitless-style selection at the board level. Its integrated DSPLL removes external analog loop components, shrinking the timing section BOM compared with discrete VCXO-plus-PLL designs.
おすすめ
Fibre Channel Storage Networks
Fibre Channel host bus adapters and storage switches require precise serial reference clocks (for example 156.25 MHz for 4x/8x rates and multiples up to 1050 MHz for faster SerDes). The SI5365-C-GQR provides any-frequency synthesis across this range with low-jitter DSPLL outputs, supporting 1x through high-rate Fibre Channel generations from a single reference architecture. Its five independent outputs can drive multiple ports or fabric switches from one timing IC, and CML/LVPECL output levels interface directly to optical module reference inputs. Designers should budget for the NRND status by qualifying the Si533x successor in parallel.
おすすめ
Optical Transport Network (OTN) Line Cards
OTN line cards combine multiple mapping clocks (such as 155.52 MHz, 622.08 MHz, and 669.3312 MHz) that must all derive from one network reference. The SI5365-C-GQR accepts four reference inputs covering 19.44 MHz to 707.35 MHz and generates five multiplied outputs up to 1050 MHz, allowing one IC to supply the full clock tree for OTU1/OTU2 framers and SerDes. The digitally controlled 150 kHz to 1.3 MHz loop bandwidth lets designers tune jitter transfer for standards compliance without changing board components, an advantage over fixed analog loop filters across process, voltage, and temperature corners.
おすすめ
High-Speed Backplane Clock Distribution
On 10G-class backplanes, a central timing card multiplies a 156.25 MHz reference and distributes low-jitter clocks to multiple blades. The SI5365-C-GQR's five differential outputs in LVPECL or LVDS levels drive point-to-point backplane clock pairs up to 1050 MHz, while its CML outputs connect directly to high-speed SerDes reference pins. Because the DSPLL integrates the VCXO and loop filter, the timing card avoids tuning analog components, and the BWSEL[1:0] pins let a single PCB design serve multiple jitter-transfer requirements by changing strap options rather than loop filter networks.
おすすめ
Test and Measurement Instruments
Bert generators, protocol analyzers, and jitter testers need selectable, low-jitter synthesized clocks across a wide frequency range. The SI5365-C-GQR's any-frequency capability from 19.44 MHz to 1050 MHz, four switchable references, and five outputs let an instrument cover multiple standard line rates from one clock section. The programmable 150 kHz to 1.3 MHz loop bandwidth supports jitter-transfer test scenarios by changing bandwidth via BWSEL[1:0] straps. For new instrument platforms, designers should evaluate the Si533x family instead, since the SI5365 is not recommended for new designs and availability depends on residual stock.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5365-C-GQR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5365-B-GQR | SI5365-A-GQR | SI5338 |
|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Max Output Frequency | 1.05 GHz | 1.05 GHz | 1.05 GHz | 710 MHz |
| Output Signal Types | CML, LVDS, LVPECL, LVCMOS | CML, LVDS, LVPECL, LVCMOS | CML, LVDS, LVPECL, LVCMOS | LVCMOS, LVDS, LVPECL |
| Lifecycle Status | NRND (not recommended for new designs) | NRND | NRND | Active (manufacturer-recommended successor) |
主な差別化要因
- Integrated DSPLL eliminates external VCXO and loop filter （vs SI5365-B-GQR)
- 1050 MHz maximum output exceeds Si5338 successor （vs SI5338)
- Pure multiplication vs jitter attenuation （vs SI5366)
設計ノート
The SI5365-C-GQR is a clock multiplier, NOT a jitter attenuator: reference jitter above the programmed loop bandwidth (150 kHz to 1.3 MHz, set via BWSEL[1:0]) passes to the outputs essentially unattenuated. If your reference is a noisy recovered clock, place an Si5366 jitter attenuator upstream or choose the Si5366 instead. Also note the part is marked not recommended for new designs; the manufacturer directs new designs to the Si533x family, so budget a qualification path before committing the SI5365 to a long-life product.
Because the DSPLL integrates the VCXO and loop filter, no external loop components are required - but each of the four differential inputs and five differential output pairs still needs 50-ohm controlled-impedance routing with the reference plane directly beneath. Keep the 100-TQFP's output pairs length-matched within a few mils for CML/LVPECL runs above 622 MHz, and use a solid, low-impedance ground pour under the device. Distributor stocking shows tape-and-reel standard quantity of 250; plan assembly scheduling accordingly for prototypes.
The Si5365 operates from multiple supply domains corresponding to its CML, LVDS/LVPECL, and LVCMOS output banks - decouple each supply pin pair with 0.1 uF ceramic capacitors placed within 2 mm of the pin, plus bulk capacitance per supply rail. CML outputs at gigahertz rates contribute the largest supply transients, so dedicate one via pair per supply pin to the ground plane. Estimated: with five differential outputs toggling near 1 GHz, ensure the analog supply rail is sourced from a low-noise LDO rather than a switching regulator to preserve the DSPLL's low-jitter output specification.
コンプライアンス情報
Compliance data was not present in the verified web data for this NRND part; consult the Skyworks product page or distributor compliance sheets (e.g., DigiKey) for current RoHS/REACH declarations.