SI5366-C-GQ - 1.05GHz Jitter Attenuator Clock Multiplier | Skyworks
部品番号: SI5366-C-GQ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.9 | $389.00 |
| 100 | $34.75 | $3,475.00 |
| 500 | $31.2 | $15,600.00 |
| 1,000 | $28.6 | $28,600.00 |
SI5366-C-GQ 概要
A jitter attenuator is a specialized clock generator built around a phase-locked loop (PLL) that cleans reference clocks by narrowing their jitter distribution while synthesizing output frequencies. Within the timing hierarchy, the Si5366 belongs to the clock multiplier and frequency synthesizer family, positioned below full network synchronization cards but above simple zero-delay buffers, and it serves as the timing backbone for synchronous optical networking (SONET), Ethernet, and Fibre Channel line cards.
Key features include selectable output frequencies from 8 kHz to 1050 MHz, third-generation DSPLL technology, an integrated loop filter with selectable loop bandwidth from 60 Hz to 8.4 kHz, four clock inputs with manual or automatic hitless switching, and output logic levels selectable among CML, CMOS, LVDS, and LVPECL. The C-grade option delivers 0.3 ps rms typical jitter generation and meets OC-192 GR-253-CORE jitter specifications, making it suitable for the most demanding telecom compliance regimes.
Technically, the DSPLL architecture replaces conventional discrete RC loop filters with an on-chip digital loop filter, enabling precise bandwidth programmability without external components and superior tolerance of noisy references. Frequency plans are configured through in-circuit programming rather than factory pin-strapping, allowing one device to serve many clocking architectures.
Typical applications include SONET OC-48/OC-192 line-card clock recovery and synthesis, 10 Gigabit Ethernet PHY reference clocking, Fibre Channel storage-area-network switching, and telecom transport equipment requiring hitless reference switching between redundant sources.
A key design consideration is power supply integrity: high-speed CML and LVPECL outputs demand clean 2.5V/3.3V rails and solid ground planes; omitting proper decoupling at the PLL supply pins degrades the sub-picosecond jitter floor.
This page synthesizes distributor pricing, drop-in alternatives, design notes, and compliance data not found in the manufacturer datasheet alone.
ドロップイン代替品: SI5366-C-GQ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5366-C-GQ （同一形状・フットプリント） — 相違点: Input Frequency Range, Output Frequency Range, Package, Maximum Output Frequency, Packaging.
クイック比較ツール — 並列比較する代替部品を選択:
SI5366-B-GQ
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
価格はお問い合わせください
データシートを見る →SI5366-A-GQ
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SI5366-C-GQR
✅ ドロップイン✓ 在庫あり
$14.22 / 個
データシートを見る →SI5369A-C-GQ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5369B-C-GQ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5366-C-GQ 仕様
| 機能 | Clock Multiplier, Jitter Attenuator |
| PLL | Yes (DSPLL, third generation) |
| Maximum Output Frequency | 1050 MHz (1.05 GHz) |
| Input Frequency Range | 8 kHz to 707 MHz |
| Output Frequency Range | 8 kHz to 1050 MHz |
| Number of Clock Inputs | 4 |
| Number of Clock Outputs | 5 |
| Jitter Generation | 0.3 ps rms typ (12 kHz to 20 MHz) |
| Output Logic Levels | CML, CMOS, LVDS, LVPECL |
| Loop Bandwidth | 60 Hz to 8.4 kHz (selectable, integrated loop filter) |
| Hitless Switching | Manual or automatically controlled |
| Standards Compliance | Meets OC-192 GR-253-CORE jitter specifications |
| パッケージ | 100-TQFP |
| 実装タイプ | Surface Mount |
SI5366-C-GQ 100-tqfp ピン配置ガイド
SI5366-C-GQ (100-tqfp パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: SI5366-C-GQ.
詳細は データシート をご参照ください。
主な用途
SI5366-C-GQ の用途: 6 件s: SONET OC-48/OC-192 Line Cards, 10 Gigabit Ethernet Switching, Fibre Channel SAN Switching, Telecom Synchronization and Timing Cards, Test and Measurement Instrumentation, Wireless Baseband and Radio Units.
SONET OC-48/OC-192 Line Cards
The SI5366-C-GQ was designed explicitly for SONET OC-48 and OC-192 transport systems, where transmit and receive clocks must satisfy ITU-T-derived GR-253-CORE jitter masks. Its C-grade 0.3 ps rms jitter generation (12 kHz to 20 MHz) provides margin against the OC-192 jitter generation limit, while the selectable 60 Hz to 8.4 kHz loop bandwidth aligns with SONET jitter transfer requirements. Four clock inputs with automatic hitless switching allow seamless transition between redundant timing references without output phase disturbance, a mandatory feature in carrier-grade line cards. The five outputs simultaneously serve the framer, SerDes, and mapper reference clocks from one cleaned timing source.
おすすめ
10 Gigabit Ethernet Switching
In 10GbE switch and router line cards, PHY and MAC reference clocks demand low phase noise to keep SerDes bit-error rates low across 64b/66b links. The SI5366-C-GQ synthesizes 156.25 MHz and 312.5 MHz LVPECL or LVDS outputs from a common reference with jitter generation as low as 0.3 ps rms, directly meeting typical 10G PHY phase-jitter mask requirements. Its any-frequency DSPLL means one inventory item covers 10GBASE-R, 40GBASE-R gear-train references, and legacy 1G timing. Automatic hitless input switching supports redundant sync-E/1588 timing sources without output glitches, and output logic-level selectability (CML, CMOS, LVDS, LVPECL) lets one part drive heterogeneous clock trees.
おすすめ
Fibre Channel SAN Switching
Fibre Channel switch fabrics require tightly controlled reference clocks at 1.0625 Gbps, 2.125 Gbps, and higher rates to sustain BER targets across retimed ports. The SI5366-C-GQ generates these Fibre Channel frequencies from a single reference using its DSPLL core, with integrated loop filter and selectable 60 Hz to 8.4 kHz bandwidth suppressing reference noise effectively. Because the datasheet explicitly lists Fibre Channel among its target systems, jitter compliance at these rates is characterized. The four-input hitless architecture also supports redundant fabric-clock cards, while five simultaneous outputs distribute timing to fabric, edge, and management ports from one device in the 100-TQFP footprint.
おすすめ
Telecom Synchronization and Timing Cards
Central-office synchronization supply units (SSUs) and BITS cards groom timing references derived from GPS, PRC, or T1/E1 spans. The SI5366-C-GQ accepts slow 8 kHz references and multiplies them to any output up to 1050 MHz, covering both legacy TDM distribution at 1.544/2.048 MHz rates and modern packet-timing PHY references. Hitless switching between four inputs protects against reference failures, and the narrow selectable loop bandwidth (down to 60 Hz) provides deep reference-noise filtering for wander-sensitive TDM output. Operating as the core of a timing card, one 100-TQFP device replaces discrete VCXO-plus-PLL chains and their manual loop-filter tuning.
おすすめ
Test and Measurement Instrumentation
Bit-error-rate testers, protocol analyzers, and jitter-tolerance test sets need programmable, ultra-clean clocks spanning thousands of standard rates. The SI5366-C-GQ's any-frequency DSPLL, programmable via serial interface, lets one instrument platform generate 8 kHz to 1050 MHz outputs on demand, including SONET/SDH, Ethernet, and Fibre Channel standard rates, with 0.3 ps rms jitter adequate as a measurement reference. Four inputs allow the instrument to lock to the device-under-test reference or an external house standard with hitless transition. The CML/LVDS/LVPECL/CMOS output selectability matches arbitrary DUT input requirements without level-shifting circuitry.
おすすめ
Wireless Baseband and Radio Units
LTE and 5G baseband cards synchronize data converters, FPGAs, and modems to a common low-jitter reference derived from fronthaul timing. The SI5366-C-GQ cleans an incoming SyncE/PTP-derived clock and synthesizes converter sampling clocks up to 1050 MHz with 0.3 ps rms jitter, preserving SNR in wideband ADCs and DACs whose aperture jitter converts to noise. Automatic hitless input switching maintains coherent timing when fronthaul references fail over. Its wide 8 kHz input acceptance also allows locking directly to slow synchronization pulses, and the selectable narrow loop bandwidth (60 Hz) suppresses packet-based phase noise before it reaches the converters.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5366-C-GQ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5366-B-GQ | SI5366-A-GQ | SI5366-C-GQR | SI5369A-C-GQ | SI5369B-C-GQ |
|---|---|---|---|---|---|---|
| Package | 100-TQFP | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Drop-in Compatibility | Reference part | Pin-to-pin, grade change only | Pin-to-pin, grade change only | Identical die, reel packaging | Requires design re-verification | Requires design re-verification |
主な差別化要因
- Best jitter grade in the Si5366 family （vs SI5366-B-GQ)
- Hitless input switching across four references （vs SI5369A-C-GQ)
- Fully integrated loop filter （vs SI5366-A-GQ)
設計ノート
The SI5366-C-GQ's 0.3 ps rms jitter floor is achievable only with disciplined power distribution. Provide separate low-noise supply domains for the DSPLL analog core and each output-bank supply, decoupling each pin with 0.1 uF ceramic capacitors placed within 2 mm, plus bulk 10 uF per rail. Ferrite beads between the digital 3.3V rail and the PLL analog supply attenuate switching-regulator spurs that would otherwise modulate output phase. Estimated: a 20 mV rms supply ripple coupling to a typical PLL supply-pushing figure produces phase spurs well above the 0.3 ps noise budget, so linear post-regulation of the PLL rail is recommended for jitter-critical designs.
On the 100-TQFP land pattern, route LVPECL/CML outputs as 100-ohm differential pairs with length matching within 5 mil and a solid, unbroken reference plane beneath. Keep input reference clock traces away from output traces to avoid crosstalk-induced jitter, and surround the device ground pins with a dense via stitch to the ground plane. Place the series termination resistors for CML/LVPECL outputs close to the driver pins. Avoid routing other clock trees or fast digital buses directly under the Si5366; the DSPLL supply pins are the most sensitive nodes on the board.
Two frequent mistakes with the Si5366: first, assuming pin compatibility with the Si5369 family - although both are 100-TQFP Skyworks DSPLL parts, the Si5369 architecture and configuration differ, and substitution requires re-verification against the datasheet. Second, ignoring the frequency-plan configuration: outputs are set by programmed divider values, not pin straps, so a board brought up with default or stale register files will run at wrong frequencies. Validate the loop-bandwidth setting against your jitter-transfer requirement - a bandwidth set too wide passes reference noise through and defeats the attenuation purpose.
コンプライアンス情報
Compliance status not stated in the retrieved source snippets; confirm via Skyworks product page or DigiKey part 2278217 before release.