Si5369 - Any-Frequency Jitter Attenuating Clock | Skyworks
部品番号: Si5369 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $22.1 | $221.00 |
| 100 | $19.6 | $1,960.00 |
| 500 | $17.4 | $8,700.00 |
| 1,000 | $15.3 | $15,300.00 |
Si5369 概要
A jitter attenuating clock multiplier (also called a jitter cleaner or precision clock IC) is a phase-locked-loop-based timing device that takes a noisy or frequency-mismatched reference clock and produces one or more ultra-clean output clocks. Within the timing hierarchy, it sits above simple clock oscillators and below full network synchronization modules, combining a digital PLL, integrated VCO, and programmable loop filter in a single clock management IC.
Key features include ultra-low jitter generation of 300 fs rms (12 kHz-20 MHz bandwidth on B/D grades), an integrated loop filter with selectable loop bandwidth, and any-frequency synthesis via Silicon Labs' dsPLL architecture that eliminates external VCXO selection. The selectable loop bandwidth allows designers to trade jitter transfer versus jitter tolerance for SONET/SDH, OTN, or Ethernet compliance.
Technically, the Si5369 uses a third-generation dsPLL (digitally synthesized PLL) with an integrated low-noise VCO and an on-chip loop filter configurable from tens of Hz to several kHz, removing the need for external loop-filter component design. Frequency plans are computed in-circuit, so a single stock part supports thousands of output/input frequency combinations, reducing BOM proliferation.
Typical applications include line-card and transport synchronization in SONET/SDH and OTN equipment, jitter cleaning for 10G/40G Ethernet PHYs, low-jitter clocking for high-speed ADC/DAC converters, and reference distribution in wireless base stations and test instrumentation.
A key design consideration is that loop bandwidth selection directly governs jitter transfer: tight bandwidths attenuate input jitter best but increase lock time, so choose the bandwidth setting per the applicable jitter tolerance mask.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: Si5369 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
SI5369B-C-GQ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5369D-C-GQ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5369A-C-GQ
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
Si5369 仕様
| Product Type | Any-frequency precision clock multiplier / jitter attenuator |
| Output Frequency Range | 2 kHz to 945 MHz (any frequency); select frequencies to 1.4 GHz |
| Input Frequency Range | 2 kHz to 710 MHz |
| Jitter Generation | 300 fs rms (typical, best grade) |
| Loop Filter | Integrated, selectable loop bandwidth |
| パッケージ | 100-TQFP |
| 実装タイプ | Surface Mount |
| Operating Temperature Min | -40 C |
| Frequency Synthesis | Any-frequency (dsPLL based) |
| Jitter Bandwidth (per grade) | 12 kHz-20 MHz or 50 kHz-80 MHz (grade dependent) |
| Evaluation Board | Si5369-EVB |
| Manufacturer | Skyworks Solutions (Silicon Labs timing product line) |
Si5369 100-tqfp ピン配置ガイド
Si5369 (100-tqfp パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: Si5369.
詳細は データシート をご参照ください。
主な用途
Si5369 の用途: 6 件s: SONET/SDH and OTN Line-Card Synchronization, High-Speed ADC/DAC Clocking, 10G/40G Ethernet PHY Reference Clock Cleaning, Wireless Base Station Timing Distribution, Test and Measurement Instrument Clocking, Optical Module and Framer Clock Generation.
SONET/SDH and OTN Line-Card Synchronization
Transport and line-card equipment must recover and retransmit timing that complies with strict jitter transfer and wander masks. The Si5369 fits this role because its any-frequency synthesis accepts recovered 2 kHz-710 MHz references directly, and its 300 fs rms output jitter plus selectable narrow loop bandwidth (integrated filter) cleans reference jitter before retransmission. In a typical design, the recovered line clock feeds one reference input, a local oscillator feeds a second, and the Si5369 generates the system timing outputs at the required rates up to 945 MHz. The narrow-bandwidth setting maximizes wander attenuation, while dual-reference support enables hitless reference switching, a key availability feature in carrier transport hardware.
おすすめ
High-Speed ADC/DAC Clocking
High-speed data converters are jitter-limited: clock aperture jitter directly raises the noise floor and caps achievable SNR. The Si5369 addresses this by multiplying a system reference to the converter sample rate - any frequency from 2 kHz to 945 MHz, with select frequencies to 1.4 GHz for higher-rate converters - while adding as little as 300 fs rms of its own jitter. Because it attenuates upstream supply and reference jitter through its narrow-bandwidth dsPLL loop, the converter sees a cleaner clock than a direct PLL multiplier chain would provide. Place it close to the converter clock input, use a low-noise supply rail, and select a loop bandwidth wide enough to lock quickly at startup but narrow enough to reject the system reference's spurious content.
おすすめ
10G/40G Ethernet PHY Reference Clock Cleaning
Ethernet PHY and MAC SERDES blocks require low-jitter 156.25 MHz-class reference clocks, yet system references are often shared, gapped, or noisy. The Si5369 generates the required rate any-frequency from a 2 kHz-710 MHz input and, with jitter generation as low as 300 fs rms, keeps the SERDES reference within typical 10G/40G eye-mask budgets. Its integrated loop filter eliminates external VCXO tuning, and the selectable bandwidth balances jitter transfer against lock time during link retraining or reference switchover. Using one stock part across multiple port speeds also simplifies line-card variants, since the frequency plan is configured digitally rather than fixed at order time, reducing inventory of speed-specific crystals or oscillators.
おすすめ
Wireless Base Station Timing Distribution
Base station cards need multiple synchronous low-jitter clocks derived from a single GPS-backed or backhaul reference. The Si5369 serves as the central timing multiplier: it accepts the recovered reference (2 kHz-710 MHz input range), attenuates its jitter with the selectable narrow loop bandwidth, and distributes clean outputs up to 945 MHz to transceivers, converters, and framer logic. The 300 fs rms jitter floor preserves EVM and phase-noise margins in the radio transceiver, and the any-frequency capability means one part supports multiple radio standards on the same PCB. Dual-reference inputs support holdover and protection switching between GPS and backhaul timing sources without redesigning the clock tree.
おすすめ
Test and Measurement Instrument Clocking
Instruments such as arbitrary waveform generators, spectrum analyzers, and BERTs require a master clock that is both flexible in frequency and extremely clean. The Si5369's any-frequency synthesis (2 kHz to 945 MHz output, select frequencies to 1.4 GHz) lets one instrument platform cover a broad output-frequency range under digital control, while 300 fs rms jitter keeps phase noise below the instrument's measurement floor. Skyworks supports evaluation with the Si5369-EVB board, accelerating frequency-plan prototyping before layout. In bench instruments, pair the Si5369 with a high-stability ovenized reference and select a narrow loop bandwidth so the instrument inherits the reference's close-in phase noise while rejecting residual switching-supply spurs.
おすすめ
Optical Module and Framer Clock Generation
Optical transport modules (XFP, SFP+, CFP-class) and their host framer ASICs need reference and word clocks at line-rate-dependent frequencies. The Si5369 multiplies the module's reference to these rates any-frequency, up to 945 MHz (select rates to 1.4 GHz), with sub-picosecond 300 fs rms jitter that meets optical-link jitter budgets. Its integrated loop filter and digital frequency-plan configuration allow a single module design to serve multiple line rates, simplifying qualification across SKUs. Because jitter attenuation also cleans the noisy host-backplane reference, the module can pass compliance testing even when the host clock quality is marginal - a common field condition that pure multipliers cannot handle.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: Si5369 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5369B-C-GQ | SI5369D-C-GQ | SI5369A-C-GQ |
|---|---|---|---|---|
| Package | 100-TQFP | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same |
| Brand | Silicon Labs (Skyworks timing) | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Output Frequency Range | 2 kHz to 945 MHz (select to 1.4 GHz) | 2 kHz to 945 MHz (select to 1.4 GHz) | 2 kHz to 945 MHz (select to 1.4 GHz) | 2 kHz to 945 MHz (select to 1.4 GHz) |
| Input Frequency Range | 2 kHz to 710 MHz | 2 kHz to 710 MHz | 2 kHz to 710 MHz | 2 kHz to 710 MHz |
| Loop Filter | Integrated, selectable bandwidth | Integrated, selectable bandwidth | Integrated, selectable bandwidth | Integrated, selectable bandwidth |
| Operating Temperature Min | -40 C | -40 C | -40 C | -40 C |
| Primary Use Case | Any-frequency jitter attenuation | Same family, B jitter grade | Same family, lowest jitter grade | Same family, entry jitter grade |
主な差別化要因
- Lowest jitter grade in family （vs SI5369B-C-GQ)
- True any-frequency synthesis （vs Fixed-frequency clock multipliers)
- Integrated loop filter （vs Discrete PLL + external VCXO solutions)
設計ノート
Precision clock ICs of this class are highly sensitive to supply noise, which converts to deterministic jitter via PSRR. Provide dedicated low-noise LDO rails for the analog PLL/VCO supply pins, separate from the digital I/O supply, and decouple each supply pin with 0.1 uF ceramic capacitors placed within 2 mm, plus bulk 10 uF per rail. Keep switching-regulator components and their loops physically distant from the Si5369. Estimated: even a few mVrms of supply ripple on a PLL supply can add tens of femtoseconds of jitter, eroding the 300 fs rms budget, so measure rail noise during validation.
Route the differential clock outputs (typically CML/LVPECL-class, per datasheet) as tightly coupled 100-ohm differential pairs with length matching within 5 mils, ground-referenced on adjacent layers. Terminate per the datasheet output format recommendations. Avoid stubs and vias on clock nets; each via adds discontinuity and potential mode conversion. Place the Si5369 close to its primary clock consumers (SERDES, ADC clock pins) rather than centralizing the clock tree, minimizing the longest high-jitter-sensitivity trace. Reference-plane continuity under the pairs is mandatory - never route clocks over plane splits.
The dominant pitfall with the Si5369 family is treating it as a fixed-frequency part: its any-frequency operation depends on a correctly computed frequency plan loaded into the device (via configuration or one-time programming). A wrong plan yields an output that appears functional but with degraded lock or jitter behavior. Second, do not select an overly wide loop bandwidth just for fast lock - it will pass input-reference jitter through and break jitter-transfer compliance. Finally, verify the exact jitter grade letter (A/B/D) on purchased parts; grades are not interchangeable in jitter-budget-driven designs even though the footprint is identical.
コンプライアンス情報
Compliance data not stated in the verified web data; consult the Skyworks product page for SI5369B-C-GQ / SI5369D-C-GQ for current RoHS/REACH declarations.