THS1230CDWR - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
部品番号: THS1230CDWR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.4 | $8.40 |
| 10 | $7.55 | $75.50 |
| 100 | $6.72 | $672.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.2 | $5,200.00 |
THS1230CDWR 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog input voltages and produces discrete digital codes at a defined sample rate. The THS1230 belongs to the successive-approximation-register (SAR) ADC product family, which trades the very high sample rates of flash or pipeline converters for low power consumption, low latency, and excellent DC accuracy. Within the broader semiconductor taxonomy, the THS1230 is a data-conversion IC, itself a sub-category of mixed-signal integrated circuits that sit between analog signal-conditioning blocks and a host microcontroller, FPGA, or DSP.
Key features of the THS1230CDWR include 12-bit resolution, 30 MSPS maximum sampling rate, configurable analog inputs that can be set to single-ended, single-ended with offset, or true differential modes, internal reference voltage, and a hardware power-down pin that drops quiescent current to microamp levels when conversions are not required. The part operates from a single 3.3 V supply and is specified over the commercial 0 °C to +70 °C temperature range (C-grade). The wide input range and flexible input topology allow the converter to interface directly with many op-amp output stages without external level translation.
Internally, the THS1230 uses a pipelined multi-stage architecture combined with an internal reference and digital error correction to deliver 12-bit linearity at high throughput while keeping total power consumption below 250 mW at full sample rate. The digital outputs are CMOS-compatible and can be directly connected to a wide range of DSPs, microcontrollers, and FPGAs. Built-in sample-and-hold, internal clock duty-cycle stabilizer, and an out-of-range indicator further simplify system design.
Typical applications include CCD and CIS imaging digitizers, baseband processing for low-IF radio receivers, portable instrumentation and data loggers, ultrasound front-end preprocessing, and general-purpose high-speed data acquisition systems. Its low power dissipation also makes it well suited to battery-powered equipment.
When designing with this device, pay close attention to the analog input common-mode voltage, the decoupling of AVDD and DRVDD supplies, and the placement of the input RC anti-aliasing network. Use a low-jitter external oscillator to drive the CLK input because aperture-jitter limitations directly cap achievable signal-to-noise ratio at high input frequencies.
This page synthesizes distributor pricing, drop-in SOIC-28 alternatives, and practical design notes that are not aggregated in any single manufacturer datasheet.
ドロップイン代替品: THS1230CDWR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: THS1230CDWR （同一形状・フットプリント） — 相違点: Architecture, Operating Temperature, Resolution, Data Interface, Input Type.
クイック比較ツール — 並列比較する代替部品を選択:
THS1230CDW
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1230CDWG4
✅ ドロップイン✓ 在庫あり
$4.85 / 個
データシートを見る →THS1230IDWR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1230CDWR 最大定格＆電気的特性
| 分解能 | 12 bits |
| Sample Rate | 30 MSPS |
| Number of Channels | 1 |
| Supply Voltage (AVDD) | 3.3 V (single supply) |
| Architecture | Pipelined / multi-stage with digital error correction |
| Input Type | Configurable: single-ended, single-ended with offset, or differential |
| Power Dissipation | <250 mW at 30 MSPS (typical) |
| Power-Down Mode | Yes (hardware PD pin) |
| Digital Output | CMOS, parallel 12-bit |
| 動作温度 | 0 °C to +70 °C (C-grade commercial) |
| パッケージ | 28-pin SOIC (DW), 7.50 mm body width, tape and reel |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Reference | Internal (external reference option) |
THS1230CDWR ピン構成
| ピン 1 | AVDD — Analog supply voltage (3.3 V) |
| ピン 2 | AGND — Analog ground |
| ピン 3 | IN+ — Differential analog input, positive |
| ピン 4 | IN- — Differential analog input, negative |
| ピン 5 | VCM — Common-mode voltage bypass |
| ピン 6 | REFT — Top reference decoupling |
| ピン 7 | REFB — Bottom reference decoupling |
| ピン 8 | REFOUT — Internal reference output |
| ピン 9 | REFIN — Reference input |
| ピン 10 | PD — Power-down control (active high) |
| ピン 11 | MODE0 — Input mode select bit 0 |
| ピン 12 | MODE1 — Input mode select bit 1 |
| ピン 13 | DRVDD — Digital output supply |
| ピン 14 | DRGND — Digital ground |
| ピン 15 | D11 — Data output bit 11 (MSB) |
| ピン 16 | D10 — Data output bit 10 |
| ピン 17 | D9 — Data output bit 9 |
| ピン 18 | D8 — Data output bit 8 |
| ピン 19 | D7 — Data output bit 7 |
| ピン 20 | D6 — Data output bit 6 |
| ピン 21 | D5 — Data output bit 5 |
| ピン 22 | D4 — Data output bit 4 |
| ピン 23 | D3 — Data output bit 3 |
| ピン 24 | D2 — Data output bit 2 |
| ピン 25 | D1 — Data output bit 1 |
| ピン 26 | D0 — Data output bit 0 (LSB) |
| ピン 27 | OTR — Out-of-range indicator |
| ピン 28 | CLK — External clock input |
主な用途
THS1230CDWR の用途: 6 件s: CCD/CIS Imaging Digitizer, Low-IF Communications Baseband, Portable Data Acquisition System, Ultrasound Front-End Preprocessing, Test & Measurement Instrumentation, Industrial Process Control Digitizer.
CCD/CIS Imaging Digitizer
The THS1230CDWR fits CCD and CIS imaging front-ends because its 30 MSPS throughput captures video-rate pixel streams at up to 30 megapixels-per-second while the configurable single-ended or differential input accepts direct coupling from CCD output stages. With <250 mW typical dissipation it suits multi-channel camera boards, and the hardware power-down pin enables duty-cycled operation between frame captures to extend battery life in portable scanners and digital microscopes.
おすすめ
Low-IF Communications Baseband
The THS1230CDWR is well suited to digitizing low-IF baseband outputs from radio receivers because its 12-bit resolution and 30 MSPS sample rate provide sufficient dynamic range for quadrature baseband at IF frequencies up to several MHz. The differential input mode rejects common-mode noise from mixers and IF filters, and the 3.3 V single-supply operation simplifies integration alongside low-voltage DSPs. Designers should pay attention to aperture jitter, which limits achievable SNR at high input frequencies.
おすすめ
Portable Data Acquisition System
For portable and battery-powered data acquisition, the THS1230CDWR delivers 30 MSPS sampling at <250 mW while the power-down mode drops quiescent current to microampere levels between triggered captures. The 28-pin SOIC package provides enough copper area to dissipate heat without external heatsinking in handheld enclosures. Single 3.3 V supply operation allows direct connection to Li-ion battery rails via a small LDO, simplifying the analog power tree in field instruments and medical telemetry devices.
おすすめ
Ultrasound Front-End Preprocessing
In ultrasound receive-channel preprocessing, the THS1230CDWR's 30 MSPS rate captures pre-beamformed RF or post-detection envelopes at baseband rates that match mid-tier medical imaging designs. The configurable input accommodates the bipolar output of time-gain-compensation (TGC) amplifiers, and the 12-bit resolution gives sufficient dynamic range for B-mode envelope detection. Designers should de-couple AVDD/DRVDD separately and place input RC anti-aliasing filters within a few millimeters of the analog input pins.
おすすめ
Test & Measurement Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers benefit from the THS1230CDWR's combination of 30 MSPS throughput and 12-bit linearity in a small SOIC-28 footprint. The internal reference and digital error correction reduce external component count, while the hardware power-down pin enables triggered single-shot captures. The wide operating temperature range of the C-grade part (0 °C to +70 °C) covers typical laboratory environments.
おすすめ
Industrial Process Control Digitizer
In industrial process-control and condition-monitoring modules, the THS1230CDWR serves as the digitization stage for vibration, acoustic, and current-sensor outputs. The differential input mode rejects common-mode noise from motor inverters and switching power stages, while the configurable input offset accommodates bipolar sensor signals without external level shifters. The hardware power-down pin supports duty-cycled multi-channel scanning that lowers system power in factory-floor monitoring nodes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: THS1230CDWR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | THS1230CDW | THS1230CDWG4 | THS1230IDWR | THS1230IPWR | THS1215IPWG4 |
|---|---|---|---|---|---|---|
| Package | SOIC-28 (DW) | SOIC-28 (DW) - same | SOIC-28 (DW) - same | SOIC-28 (DW) - same | TSSOP-28 (PW) - smaller | TSSOP-28 (PW) - smaller |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sample Rate | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 15 MSPS |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | 0 °C to +70 °C (C-grade) | 0 °C to +70 °C | 0 °C to +70 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Power-Down Pin | Yes | Yes | Yes | Yes | Yes | Yes |
| Differential Input | Yes (configurable) | Yes | Yes | Yes | Yes | Yes |
| Packaging Media | Tape and Reel | Tube | Tube (Pb-free) | Tape and Reel | Tape and Reel | Tube |
主な差別化要因
- Lower-cost tube-packaging drop-in variant （vs THS1230CDW)
- Extended industrial temperature range drop-in （vs THS1230IDWR)
- Higher sample rate at same resolution （vs THS1215IPWG4)
設計ノート
Estimated power dissipation at 30 MSPS and 3.3 V supply is approximately 70 mA total supply current (AVDD + DRVDD combined), giving under 250 mW typical. Decouple AVDD with a 10 µF bulk capacitor in parallel with a 0.1 µF ceramic placed within 5 mm of the AVDD pin. Tie DRVDD to the same 3.3 V rail or to a separate 1.8 V logic rail through a ferrite bead; both grounds must connect at a single star point beneath the package.
Drive the CLK input with a low-jitter clock source (aperture jitter < 2 ps RMS) to preserve SNR at high analog input frequencies. Use a series termination resistor (typically 22 Ω to 33 Ω) close to the clock driver to damp overshoot. Keep the CLK trace short and routed over a continuous ground plane; cross-coupling from digital outputs D0-D11 back into IN+ or IN- will degrade harmonic performance.
Place the input anti-aliasing RC network (typically 50 Ω series + 20 pF shunt to AGND) within 5 mm of the IN+ and IN- pins. Route analog inputs as a matched differential pair on the top layer with ground-side shielding. Keep the digital outputs (D0-D11, OTR) routed away from IN+/IN- to minimize digital feedback. Connect the exposed pad (if present in DW package variant) to a clean analog ground pour for thermal relief.
Do not leave the MODE0/MODE1 pins floating; tie them to AGND or DRVDD through a defined logic level to select the intended input configuration. Failure to drive MODE pins selects an undefined state that can produce non-linear codes. Similarly, do not float the PD pin; tie it to AGND if power-down is unused, otherwise the part may enter an unintended low-power mode at power-up.
コンプライアンス情報
RoHS and REACH compliance status inferred from current TI product page status; AEC-Q100 not applicable for ADC product family. Pb-free G4 variant available for fully Pb-free assembly. Conflict-minerals declaration on file with TI.
