XDPE12284C0000XTMA1 - 8-Phase Dual Loop Digital Multiphase Controller | Infineon
部品番号: XDPE12284C0000XTMA1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.95 | $7,950.00 |
XDPE12284C0000XTMA1 概要
A digital multiphase controller is a specialized power management IC (PMIC) that drives multiple parallel power stages to deliver high currents with fast transient response. Multiphase controllers belong to the broader hierarchy of switching voltage regulators, which sit under DC-DC converters and the power management IC category. By interleaving phases at staggered clock edges, multiphase controllers reduce input/output ripple, distribute thermal load, and enable dynamic phase shedding for light-load efficiency.
Key features of the XDPE12284C include 8-phase operation, dual-loop digital control, support for Intel VR13/VR13HC rev 1.3, IMVP8 rev 1.2, and IMVP9 rev 1.3 DC-DC converter specifications, integrated SVID and PMBus interfaces, and per-rail output voltage programmability across the 0.2 V to 3.04 V range. The controller is engineered to deliver high-core-count CPU and GPU power rails with sub-millisecond transient response.
The device implements a digital control loop architecture, replacing traditional analog compensation with firmware-driven state machines and ADC-based feedback. This allows Infineon's GUI and PMBus commands to tune loop compensation, fault thresholds, and telemetry without external component changes, while maintaining tight regulation across wide load steps typical of compute workloads.
Typical applications include VR13/VR13HC server core rails, IMVP8/IMVP9 workstation VCCIN, high-end desktop CPU cores, AI accelerator cards, and HPC accelerator boards. The 8-phase capability scales to deliver tens-to-hundreds of amps when paired with Infineon DrMOS power stages such as the TDA21472 or OptiMOS power stages.
When designing with this controller, pay close attention to PCB layout symmetry between phase nodes, use low-ESL ceramic input capacitors near each phase, and follow Infineon's reference design for current-sense resistor placement. Telemetry configuration via PMBus must be validated against platform firmware before mass production.
This page synthesizes distributor pricing, package-level drop-in alternatives, and practical design notes that go beyond what is printed in the manufacturer datasheet, giving procurement and design engineers a single source for sourcing and replacement decisions.
ドロップイン代替品: XDPE12284C0000XTMA1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: XDPE12284C0000XTMA1 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Product Type, RoHS Status, Number of Outputs.
クイック比較ツール — 並列比較する代替部品を選択:
XDPE12284C0000XUMA1
✅ ドロップイン✓ 在庫あり
$3.72 / 個
データシートを見る →XDPE12284D0000XTMA1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XDPP1148100BXUMA1
✅ ドロップイン✓ 在庫あり
$5.25 / 個
データシートを見る →XDPP1140100BXUMA1
✅ ドロップイン✓ 在庫あり
$4.2 / 個
データシートを見る →IR2304SPBF
✅ ドロップイン✓ 在庫あり
$0.48 / 個
データシートを見る →XDPE12284C0000XTMA1 最大定格＆電気的特性
| Product Type | Digital Multiphase Controller |
| トポロジー | Dual-Rail 8-Phase |
| 出力数 | 2 |
| 出力電圧範囲 | 0.2 V to 3.04 V |
| Number of Phases | 8 (total across both rails) |
| Control Loop | Digital dual-loop |
| Intel Specification Compliance | VR13 rev 1.3, VR13HC rev 1.3, IMVP8 rev 1.2, IMVP9 rev 1.3 |
| SVID Protocol | Intel SVID rev 1.9.1 compliant |
| PMBus Interface | PMBus rev 1.3 compliant |
| パッケージ | PG-VQFN-40-13 |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
XDPE12284C0000XTMA1 ピン構成
| ピン 1 | PWM1A — Phase 1 PWM output Rail A |
| ピン 2 | PWM1B — Phase 1 PWM output Rail B |
| ピン 3 | PWM2A — Phase 2 PWM output Rail A |
| ピン 4 | PWM2B — Phase 2 PWM output Rail B |
| ピン 5 | PWM3A — Phase 3 PWM output Rail A |
| ピン 6 | PWM3B — Phase 3 PWM output Rail B |
| ピン 7 | PWM4A — Phase 4 PWM output Rail A |
| ピン 8 | PWM4B — Phase 4 PWM output Rail B |
| ピン 9 | VCC — Controller supply voltage |
| ピン 10 | AGND — Analog ground |
| ピン 11 | CS1A — Current sense input phase 1 Rail A |
| ピン 12 | CS1B — Current sense input phase 1 Rail B |
| ピン 13 | CS2A — Current sense input phase 2 Rail A |
| ピン 14 | CS2B — Current sense input phase 2 Rail B |
| ピン 15 | TSEN_A — Temperature sense input Rail A |
| ピン 16 | TSEN_B — Temperature sense input Rail B |
| ピン 17 | VR_RDY — Voltage ready output |
| ピン 18 | ENABLE — Controller enable input |
| ピン 19 | SVID_CLK — SVID clock input |
| ピン 20 | SVID_DAT — SVID data I/O |
| ピン 21 | SVID_ALRT — SVID alert output |
| ピン 22 | PMB_CLK — PMBus clock input |
| ピン 23 | PMB_DAT — PMBus data I/O |
| ピン 24 | PMB_ALRT — PMBus alert output |
| ピン 25 | VSEN_A_P — Voltage sense positive Rail A |
| ピン 26 | VSEN_A_N — Voltage sense negative Rail A |
| ピン 27 | VSEN_B_P — Voltage sense positive Rail B |
| ピン 28 | VSEN_B_N — Voltage sense negative Rail B |
| ピン 29 | VBOOT_A — Boot voltage Rail A |
| ピン 30 | VBOOT_B — Boot voltage Rail B |
| ピン 31 | PGOOD_A — Power good Rail A |
| ピン 32 | PGOOD_B — Power good Rail B |
| ピン 33 | FAULT_A — Fault output Rail A |
| ピン 34 | FAULT_B — Fault output Rail B |
| ピン 35 | ADDR — SVID/PMBus address select |
| ピン 36 | CONFIG — Configuration strap input |
| ピン 37 | RESET — Digital reset input |
| ピン 38 | TEST — Factory test pin |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | EP — Exposed thermal pad, connect to AGND |
主な用途
XDPE12284C0000XTMA1 の用途: 6 件s: Intel VR13 Server Core Rail, IMVP8/IMVP9 Workstation VCCIN, High-End Desktop CPU VR, AI Accelerator Card Power, HPC Accelerator Board VR, Datacenter Server Motherboard.
Intel VR13 Server Core Rail
The XDPE12284C drives the VCCIN rail of Intel VR13/VR13HC server CPUs by sequencing 4-8 phases across two rails, with output voltage digitally programmed from 0.2 V to 3.04 V via SVID rev 1.9.1 commands. The 8-phase capability scales to deliver the 100-200 A transient currents that high-core-count Xeon-class processors demand, while the digital loop maintains sub-1% regulation under load steps. Per Infineon reference designs, pairing with TDA21472 DrMOS stages on each phase yields >90% peak efficiency at full load.
おすすめ
IMVP8/IMVP9 Workstation VCCIN
For Intel IMVP8 and IMVP9 workstation CPUs, the XDPE12284C's dual-loop architecture maps Rail A to VCCIN and Rail B to VCCSA, with independent SVID address assignments. The 0.2 V to 3.04 V output range covers the entire IMVP9 voltage envelope including low-voltage deep-sleep states at 0.25 V. According to the Infineon datasheet, PMBus rev 1.3 telemetry reports per-rail voltage, current, and temperature to the platform BMC for predictive failure analysis.
おすすめ
High-End Desktop CPU VR
In enthusiast desktop motherboards, the XDPE12284C drives the VCore and VCCGT rails of overclocked CPUs with 6+2 phase assignments across its two rails. The SVID rev 1.9.1 interface accepts dynamic VID changes from the CPU in microseconds, supporting Intel Turbo Boost transitions without output-voltage droop. Per the verified datasheet, the digital loop compensation eliminates the external RC networks required by analog controllers, simplifying PCB layout for high-density ATX boards.
おすすめ
AI Accelerator Card Power
AI accelerator cards (GPUs, TPUs, custom ASICs) require multi-rail power delivery with PMBus telemetry for power capping and thermal management. The XDPE12284C's two programmable rails deliver VDD and VDDQ for high-current ASIC loads, with the PMBus rev 1.3 interface reporting per-rail power consumption to the host BMC for workload-aware power budgeting. The 8-phase digital control enables sub-millisecond transient response for tensor-pipeline load steps.
おすすめ
HPC Accelerator Board VR
HPC accelerator boards host multiple high-current ASICs that each require their own VDD/VCCINT rail. The XDPE12284C's two-rail output drives one ASIC's main rail and a second ASIC's auxiliary rail on the same board, reducing BOM cost versus two separate controllers. According to Infineon reference designs, the digital controller's phase-shedding capability drops inactive phases at light load to maintain >85% efficiency even when one accelerator is idle.
おすすめ
Datacenter Server Motherboard
Datacenter server motherboards integrate CPU and chipset VRs on a single PCB where the XDPE12284C drives both VCCIN and a secondary SoC rail. The PG-VQFN-40-13 small footprint enables high-density server board layouts, while Infineon's PMBus rev 1.3 implementation supports platform-level power telemetry required by OCP and Open Compute standards. Per the verified datasheet, fault protection includes OVP, OCP, and thermal shutdown with PMBus-monitored status registers.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: XDPE12284C0000XTMA1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | XDPE12284C0000XUMA1 | XDPE12284D0000XTMA1 | XDPP1148100BXUMA1 |
|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon |
| Package | PG-VQFN-40-13 | PG-VQFN-40-13 - same | PG-VQFN-40-13 - same | PG-VQFN-40 - same family |
| Number of Phases | 8 (dual-rail) | 8 (dual-rail) | 8 (dual-rail) | 14 (single/dual) |
| Number of Outputs | 2 | 2 | 2 | 2 |
| Output Voltage Range | 0.2 V to 3.04 V | 0.2 V to 3.04 V | 0.2 V to 3.04 V | 0.2 V to 3.04 V |
| Intel Spec Compliance | VR13/VR13HC/IMVP8/IMVP9 | VR13/VR13HC/IMVP8/IMVP9 | VR13/VR13HC/IMVP8/IMVP9 (newer rev) | VR13/IMVP8/IMVP9 |
| SVID Protocol | SVID rev 1.9.1 | SVID rev 1.9.1 | SVID rev 1.9.1 | SVID rev 1.9.1 |
| PMBus Interface | PMBus rev 1.3 | PMBus rev 1.3 | PMBus rev 1.3 | PMBus rev 1.3 |
| Control Loop | Digital dual-loop | Digital dual-loop | Digital dual-loop | Digital dual-loop |
主な差別化要因
- Dual-loop digital control with per-phase telemetry （vs XDPP1148100BXUMA1)
- Pin-compatible newer silicon revision available （vs XDPE12284D0000XTMA1)
- Same package as higher-phase XDP siblings （vs XDPP1140100BXUMA1)
設計ノート
Symmetrical phase-node routing is critical for multiphase controllers. Per Infineon reference designs, keep all phase-node copper shapes (input cap to phase node to DrMOS to output cap) equal-length to within 50 mils to ensure proper current sharing across phases. Place current-sense resistors close to the phase inductor return path and use Kelvin connections back to the controller's CS pins to avoid ground-loop errors.
Separate analog and digital grounds on the PCB using a split-plane approach, joining them only at the controller's AGND pin. The PG-VQFN-40-13 exposed thermal pad must be soldered to a copper pour connected to AGND for both thermal dissipation and ground reference. Per the Infineon datasheet, the exposed pad reduces thermal resistance and provides the primary heat-dissipation path; missing solder connections here will trigger thermal-shutdown faults under load.
Do not connect PMBus pull-ups to a rail that powers up before the controller's VCC; this can latch the PMBus bus during controller startup and prevent SVID enumeration. According to Infineon application notes, PMBus pull-ups should be tied to the controller's VCC rail or a rail that comes up simultaneously. Also, verify SVID address strap configuration before PCB fab - the ADDR pin selects between two SVID addresses and mistakes here cause platform boot failures.
PWM traces from the controller to each DrMOS must be length-matched and routed over a continuous ground plane to prevent duty-cycle distortion at switching frequencies above 1 MHz. For 8-phase operation, route PWM1-PWM8 in a star topology from the controller to each phase rather than daisy-chaining. Estimated: at 1.5 MHz switching frequency, every 1 inch of unmatched trace adds ~17 ps delay, which over 8 phases accumulates into significant phase-offset error if not corrected.
コンプライアンス情報
RoHS compliant per Infineon product page. Industrial grade (-40C to +85C); not AEC-Q100 qualified. Halogen-free status not explicitly stated in verified data.
