ADC/DAC
제품 (2518)
HI5767/2IAZ - 10-Bit 20MSPS ADC w/ Vref, 28-SSOP | Renesas
The Renesas HI5767/2IAZ is a monolithic 10-bit analog-to-digital converter fabricated in a CMOS process, sampling at 20/40/60 MSPS with an internal voltage reference, housed in a 28-pin SSOP (Shrink Small Outline Package) for industrial-temperature applications. It is a pipelined single-input ADC designed for high-speed signal acquisition where wide bandwidth and low power consumption are essential. The internal bandgap-style reference and integrated sample-and-hold simplify board design and reduce external component count in cost-sensitive systems. An ADC (analog-to-digital converter) is a data-converter integrated circuit that samples continuous analog voltages and produces a discrete digital code proportional to the input. Within the broader taxonomy, the HI5767 belongs to pipelined ADCs (sub-class of Nyquist-rate ADCs) -> data converters -> signal-chain ICs -> mixed-signal semiconductors. Pipelined ADCs trade slightly higher latency for high sample rates and low per-conversion power, making them the workhorse of video, imaging, communications, and instrumentation front ends. Key features of the HI5767/2IAZ include 10-bit resolution, single +5 V analog supply, internal 2.5 V reference, TTL/CMOS-compatible digital outputs, and a 28-SSOP industrial-temperature (-40C to +85C) package. The pipelined architecture supports throughputs of 20, 40, or 60 MSPS, selectable via part suffix, and the low input capacitance (~5 pF) eases the design of the driving amplifier network. Differential nonlinearity (DNL) is typically within +/-0.5 LSB, ensuring no missing codes at 10 bits. Typical applications include digital video, set-top box and graphics digitizers, CCD imaging front ends, cable modem upstream/downstream IF digitizers, medical ultrasound receivers, and general-purpose high-speed data acquisition cards. The wide input bandwidth and low power (~140 mW at 60 MSPS) suit portable and line-powered designs alike. The internal reference eliminates the need for an external reference IC, saving board area and BOM cost. When designing with this part, observe the recommended single-point grounding scheme, decouple AVDD and DVDD separately with 0.1 uF + 10 uF capacitors, and drive the analog input with a low-impedance, bandwidth-appropriate op-amp such as the HA5024 or AD8055. A small RC anti-alias filter at the input is typically required. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
HI5767/4CA - 10-Bit 60MSPS ADC w/ Internal VREF | Intersil
The Intersil (now Renesas) HI5767/4CA is a monolithic 10-bit analog-to-digital converter fabricated in a CMOS process, offering 20/40/60 MSPS sampling rates with an internal voltage reference in a 28-pin SSOP/QSOP (PDSO28) package. It features a pipelined architecture, single analog input channel, and parallel word output, designed for high-speed applications where wide bandwidth and low power consumption are essential per the manufacturer datasheet. What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage converter that uses several low-resolution sub-ADCs and DACs in cascade to achieve higher overall resolution at high sampling rates. Pipelined ADCs sit between successive-approximation (SAR) ADCs and flash ADCs in the converter hierarchy, offering the best trade-off between speed, resolution, and power dissipation for sample rates between a few MSPS and a few hundred MSPS, dominating the 8-to-16-bit, 10-to-200 MSPS market. Key features of the HI5767/4CA include selectable 20, 40, or 60 MSPS operation, integrated bandgap voltage reference, CMOS-compatible digital inputs, low-power CMOS process, and analog input bandwidth suitable for IF undersampling. The part supports single +5V analog supply operation per the datasheet, and its 28-SSOP/QSOP package provides a compact footprint for instrumentation and communications designs. The pipelined architecture delivers 10-bit resolution with no missing codes and differential nonlinearity within +/-1 LSB typical. The CMOS sub-micron process enables the HI5767/4CA to combine wide analog input bandwidth (specifying suitability for undersampling applications above Nyquist) with low power dissipation, making it well-suited for battery-powered or thermally constrained systems. The internal reference eliminates external reference components and reduces PCB area while simplifying power-supply design. Typical applications include digital oscilloscopes, IF sampling for communications receivers, CCD imaging front-ends, medical ultrasound front-ends, and radar/sonar baseband digitizers. The selectable sample rate (20/40/60 MSPS) lets one hardware platform cover multiple end-product SKUs without redesign. When designing with this part, ensure analog and digital grounds are separated at the IC and joined at a single point to preserve SFDR. Decouple AVDD and DVDD independently with 0.1 uF ceramic capacitors placed as close to the pins as possible. Source-impedance matching at the analog input is critical for full-bandwidth performance. This page synthesizes distributor pricing, drop-in-compatible alternative sources, and practical design notes not consolidated in any single manufacturer document.
HI5767/4CAZ - 10-Bit 40MSPS ADC, CMOS, 28-SSOP | Renesas
The Renesas HI5767/4CAZ is a monolithic 10-bit analog-to-digital converter (ADC) fabricated in a CMOS process, sampling at up to 40 MSPS in a 28-pin SSOP/QSOP package with internal voltage reference. It supports single +5V analog supply operation and delivers pipelined, fully-differential conversion architecture with on-chip sample-and-hold and bandgap voltage reference. An analog-to-digital converter (ADC) is a data-acquisition integrated circuit that converts real-world analog signals into discrete digital codes for processing by microcontrollers, DSPs, FPGAs, or ASICs. The HI5767 family sits in the converter hierarchy as follows: ADC -> data converter -> data-acquisition IC -> mixed-signal semiconductor. Pipelined ADCs like the HI5767 use multiple low-resolution stages to achieve high sample rates while keeping per-stage power dissipation modest, making them well suited for intermediate-frequency (IF) sampling, video digitisation, and instrumentation. Key features of the HI5767/4CAZ include 40 MSPS maximum sampling rate, 10-bit resolution, internal 2.5V bandgap voltage reference, single 5V analog supply, and CMOS/TTL-compatible digital outputs. The pipelined architecture with internal sample-and-hold delivers wide input bandwidth and low power consumption relative to flash converters of equivalent speed, and the SSOP-28 footprint allows compact PCB placement for multi-channel designs. Typical applications for the HI5767/4CAZ include digital oscilloscopes, IF-sampling communications receivers, CCD/CIS imaging signal chains, medical ultrasound front ends, and industrial inspection cameras. Designers choose this part when a small-footprint 10-bit, 40 MSPS ADC with internal reference and single-supply operation is needed. Designers should observe standard high-speed mixed-signal layout practice: decouple AVDD with 0.1uF and 10uF ceramics placed within 5 mm of the supply pin, keep analog and digital ground planes separate and join them at a single point near the ADC, and drive the analog input through an AC-coupling network or low-impedance buffer to preserve SFDR. The internal reference eliminates external reference noise pick-up but constrains absolute accuracy to about +/-25 mV initial tolerance. This page synthesizes distributor pricing, datasheet pinout, drop-in same-package alternatives, and practical layout notes not consolidated in the Renesas datasheet, helping engineers shorten the evaluation cycle.
HI5767/4CB-T - 10-Bit 40MSPS Pipelined ADC | Renesas | 28-SOIC
The Renesas HI5767/4CB-T is a monolithic 10-bit pipelined analog-to-digital converter (ADC) with 40 MSPS sampling rate, integrated voltage reference, and TTL-compatible digital outputs, housed in a 28-pin SOIC (Wide) package on tape-and-reel. Designed in CMOS, the part supports the HI5767 family of 20/40/60 MSPS pin-compatible variants with 1 channel input and parallel output, targeting wideband, low-power signal acquisition. An ADC (analog-to-digital converter) is a data-converter integrated circuit that samples a continuous analog waveform and quantizes each sample to a binary code word; the ADC is a member of the data-converter IC family, which sits inside the broader power-management and signal-chain semiconductor taxonomy. Pipelined ADCs specifically use a multi-stage switched-capacitor architecture with per-stage flash sub-converters to achieve sample rates from a few MSPS to >100 MSPS while maintaining 8-14 bit resolution and small die area. Key features include an internal 2.5 V bandgap voltage reference, a single +5 V analog supply operation, and low-power CMOS design. The /4 speed-grade selects the 40 MSPS tier within the HI5767 family (the same die supports 20/40/60 MSPS via speed-grade ordering). TTL/CMOS-compatible outputs ease interface to FPGAs, ASICs, and microcontrollers without level translators. The pipelined architecture delivers consistent dynamic performance across the full Nyquist band; the CMOS process keeps typical power consumption low enough for multi-channel instrumentation boards and portable imaging designs. Internal reference trimming reduces external component count, simplifying BOM and improving accuracy. Typical applications include digital video processing, medical imaging front-ends, communications base-band signal capture, and IF/RF downconversion sampling. The wide 28-SOIC footprint supports both hand-prototype and high-volume assembly lines. Engineers choose this part when 10-bit dynamic range at 40 MSPS is sufficient and the integrated reference cuts BOM. When laying out the PCB, keep analog input traces short and symmetric to preserve SNR, and place the internal reference decoupling capacitor as close as possible to the supply pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
HI5767/4CBZ - 10-Bit 40MSPS ADC with Internal Vref | Renesas
The Renesas (formerly Intersil) HI5767/4CBZ is a monolithic 10-bit analog-to-digital converter fabricated in a CMOS process, designed for high-speed applications where wide bandwidth and low power consumption are essential. It supports sampling rates of 20/40/60 MSPS and is housed in a 28-pin SOIC (W) wide-body package, delivering pipelined conversion with an internal voltage reference and parallel digital output interface. An ADC (Analog-to-Digital Converter) is a mixed-signal data conversion IC that translates continuous analog input voltages into discrete digital codes. As a pipelined flash ADC, the HI5767/4CBZ uses a multi-stage architecture to achieve high sample rates while maintaining low power consumption, occupying the middle ground between full-flash converters (faster, more power) and successive-approximation ADCs (slower, less power). Within the broader component hierarchy, this device belongs to: data converter -> ADC -> pipelined ADC -> high-speed ADC -> mixed-signal IC -> semiconductor. Key specifications include 10-bit resolution, a 40 MSPS typical sampling rate, single +5V analog supply operation, internal 2.5V bandgap voltage reference, low-power CMOS architecture, and a parallel CMOS-compatible digital output bus. The device supports both internal and external reference modes, providing flexibility for precision and drift-critical designs. It features an input bandwidth suitable for IF undersampling and video-speed applications, and the CMOS fabrication process ensures low power dissipation (typically under 200 mW) compared to bipolar flash converters of similar speed. Typical applications include digital video processing, high-speed instrumentation, IF sampling in communications receivers, medical imaging front-ends, radar signal processing, and digital oscilloscopes. The internal reference eliminates the need for an external reference IC in cost-sensitive designs, while the parallel output bus simplifies interface to FPGAs and ASICs. The wide SOIC-28 package footprint allows hand-solderable prototyping and rework-friendly manufacturing compared to fine-pitch QFN alternatives. When designing with the HI5767/4CBZ, ensure the analog input is driven from a low-impedance, wideband buffer (such as a high-speed op-amp) to avoid aperture jitter and maintain SNR at the rated sampling rate. Decouple AVDD and DVDD separately to prevent digital switching noise from coupling into the analog input path. Use controlled-impedance PCB layout techniques for the analog input trace to preserve bandwidth and minimize reflections at high input frequencies. This page synthesizes distributor pricing, drop-in Renesas/Intersil alternatives, and practical design notes not consolidated in any single datasheet.
HI5767/4CBZ-T - 10-Bit 40MSPS ADC w/ VREF, SOIC-28 | Renesas
The Renesas HI5767/4CBZ-T is a monolithic 10-bit analog-to-digital converter fabricated in a CMOS process, sampling at 40 MSPS, and housed in a 28-pin SOIC (0.295 inch, 7.50 mm body width) package supplied on cut-tape reel. It accepts single-ended or differential inputs, provides parallel CMOS output data, integrates an internal voltage reference, and operates from a single 5 V analog supply at commercial 0C to 70C temperature grade. An analog-to-digital converter (ADC) translates continuous analog signals into discrete digital codes; the HI5767/4CBZ-T is a 10-bit pipelined flash-style converter, sitting between 8-bit general-purpose ADCs and 12/14-bit precision converters in the data-converter taxonomy. Pipelined ADCs use cascaded low-resolution stages to achieve high sample rates with low power, making them well suited to digitising IF, video, and baseband waveforms in communications and instrumentation. Key features include 10-bit resolution, 40 MSPS guaranteed sampling rate, internal 2.5 V voltage reference, single +5 V supply operation, low-power CMOS process, parallel CMOS-compatible digital interface, and an integrated sample-and-hold front end. The device is specified across the commercial 0C to 70C ambient range and supports 28-SOIC PCB mounting for high-density board layouts. Architecturally, the HI5767/4CBZ-T uses a multi-stage pipeline with on-chip sample-and-hold to support full Nyquist bandwidth at the rated 40 MSPS. Its CMOS process reduces power dissipation relative to bipolar flash ADCs, while the internal reference eliminates an external reference component and the associated layout-induced drift. Typical applications include digital video broadcast equipment, IF sampling in digital receivers, cable-modem and set-top-box downstream demodulation, CCD imaging digitisation, and general-purpose data acquisition in instrumentation. The combination of moderate resolution, high sample rate, and integrated reference is well matched to cost-sensitive consumer and industrial designs. When designing with this device, ensure adequate bypassing (a 0.1 uF ceramic in parallel with a 10 uF tantalum) close to the supply pins, and route the analog input traces as a 50 ohm microstrip if digitising signals above 20 MHz. The internal reference does not require external load capacitance, but pin REF should be decoupled with 0.1 uF to minimise kickback noise. This page synthesises distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
HI5767/6CA - 10-Bit 60MSPS ADC w/ Reference | SSOP-28 | Renesas
The Renesas HI5767/6CA is a monolithic 10-bit analog-to-digital converter fabricated in a CMOS process, designed for high-speed applications where wide bandwidth and low power consumption are essential. It delivers up to 60 MSPS conversion rate, integrates an internal voltage reference, and is housed in a 28-pin SSOP package. The pipelined architecture provides single-channel conversion with parallel CMOS-compatible digital outputs. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, enabling real-world signals (voltage, current, temperature, RF) to be processed by digital systems such as FPGAs, DSPs, and microcontrollers. Within the data-converter hierarchy, the HI5767/6CA belongs to the successive-approximation/pipelined SAR-ADC family, which occupies the middle ground between slow, high-resolution SAR converters and very high-speed flash converters. It is widely used in cost-sensitive mid-bandwidth systems where 8-10 bit resolution is sufficient. Key features of the HI5767/6CA include a 60 MHz maximum sampling rate, 10-bit resolution, internal 2.5 V voltage reference, single +5 V analog supply operation, and low power CMOS design. The pipelined architecture multiplies conversion throughput while keeping per-sample latency short, and the parallel digital interface simplifies downstream FPGA or ASIC capture. Internal reference and integrated sample-and-hold reduce the external BOM to a small number of bypass capacitors and a single decoupling network. Typical applications include video digitisation, IF sampling in communications receivers, CCD imaging front-ends, instrumentation and digital oscilloscope front-ends, and high-speed data acquisition cards. The combination of internal reference, low pin count, and 60 MSPS throughput makes the part attractive for legacy designs in industrial imaging and communications infrastructure where a 10-bit conversion is adequate. Designers should observe single-supply +5 V operation, provide adequate power-supply decoupling, and ensure the analog input drive network maintains the rated input bandwidth at the full-scale input of the converter. The wide SSOP-28 footprint simplifies PCB routing on multi-layer boards. This page synthesises distributor pricing, drop-in alternatives, and design considerations not found in the manufacturer datasheet alone, helping engineers select, qualify, and source the HI5767/6CA efficiently.
HI5767/6CAZ - 10-Bit 60MSPS ADC w/ Internal VREF | Renesas
The Renesas HI5767/6CAZ is a monolithic 10-bit, 60 MSPS analog-to-digital converter fabricated in a CMOS process, designed for high-speed applications where wide bandwidth and low power consumption are essential. It integrates an internal voltage reference, a pipelined flash architecture, and sample-and-hold input circuitry, delivering full 10-bit resolution at sampling rates up to 60 MSPS. Housed in a 28-pin SSOP/QSOP package, the /6CAZ suffix denotes the 60 MSPS grade with commercial temperature range and internal 2.5 V bandgap reference. An analog-to-digital converter (ADC) is a data-acquisition mixed-signal IC that samples a continuous analog waveform and produces a discrete digital code for downstream digital signal processing. The 10-bit pipelined flash architecture used in the HI5767 family sits hierarchically between SAR converters (slower, lower power) and full-flash converters (faster, higher power), balancing speed and die area. ADCs of this class belong to the broader family of data-converter ICs within signal-chain semiconductors, used wherever analog sensors interface with digital processors, FPGAs, or microcontrollers. Key features of the HI5767/6CAZ include 60 MSPS maximum sampling rate, 10-bit resolution, internal voltage reference eliminating external reference components, single +5 V analog supply operation, and TTL/CMOS-compatible digital outputs. The pipelined architecture provides low-latency conversion suitable for real-time signal processing, while the integrated sample-and-hold front end minimizes aperture uncertainty and supports full Nyquist-bandwidth analog input frequencies. From an architecture standpoint, the pipelined flash topology breaks the conversion into cascaded low-resolution stages, each stage resolving a subset of bits while driving a residue into the next stage. This approach achieves higher sampling rates than successive-approximation (SAR) converters at the cost of pipeline latency (typically 2-3 clock cycles). The internal voltage reference reduces external component count and improves power-supply noise rejection on the reference node. Typical applications include digital video processing, high-speed data acquisition systems, CCD imaging digitizers, communications IF baseband sampling, and professional video broadcast equipment. The /6 speed grade (60 MSPS) targets standard-definition digital video (BT.601 at 27 MHz oversampled) and intermediate-frequency sampling in digital receivers. When designing with this device, ensure the analog input drive network has 50 ohm source impedance to match the track-and-hold, decouple AVDD and DVDD with separate 0.1 uF + 10 uF capacitors placed within 5 mm of the supply pins, and respect the tRPD and tOD timing relationships between encode clock and output data. The internal reference output requires a 0.1 uF + 10 uF bypass network on the REFOUT pin. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes - including PCB layout, decoupling topology, and clock-distribution guidance - that are not consolidated in any single manufacturer datasheet or distributor listing.
HI5767/6CB - 10-Bit 60MSPS ADC, CMOS, SOIC-28 | Renesas
The Renesas HI5767/6CB is a monolithic 10-bit, 60 MSPS analog-to-digital converter fabricated in a CMOS process, housed in a 28-pin SOIC package. The HI5767/6CB integrates an internal voltage reference and a pipelined architecture that delivers 20/40/60 MSPS sampling rates with 10-bit resolution. According to the manufacturer datasheet, the device is engineered for high-speed applications where wide bandwidth and low power consumption are essential, making it suitable for digital video, communications, and instrumentation designs. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog input signals into discrete digital output codes for downstream processing. Within the broader semiconductor taxonomy, ADCs sit inside data converters, which fall under the mixed-signal IC family and ultimately under the integrated circuit (IC) hierarchy. Pipelined ADCs such as the HI5767/6CB segment the conversion into cascaded low-resolution stages, achieving a balance between speed, resolution, and power that earlier flash or successive-approximation architectures could not match. Key features of the HI5767/6CB include a maximum sampling rate of 60 MSPS, an integral non-linearity (INL) typical figure within the 10-bit class, differential or single-ended analog inputs, and CMOS-compatible digital outputs. The wide input bandwidth supports IF undersampling for communications systems, while a low-power CMOS implementation keeps thermal dissipation in check even at the top sampling speed. An internal reference reduces external component count, simplifying board layout. The pipelined architecture of the HI5767/6CB employs multi-stage switched-capacitor design with dedicated sample-and-hold and quantization stages; this architecture gives high throughput with controlled latency and supports continuous sampling at full clock rate. The CMOS process grants low dynamic power consumption relative to bipolar alternatives, an important consideration for dense multi-channel designs. Typical applications for the HI5767/6CB include digital video broadcast equipment, intermediate-frequency (IF) signal processing in communications receivers, medical imaging front-ends, and general-purpose data-acquisition systems. The part is also frequently deployed in industrial imaging, where 10-bit resolution and 60 MSPS throughput are sufficient for cost-sensitive designs. When designing with the HI5767/6CB, ensure the analog input network is bandwidth-limited to half the sampling rate (Nyquist) to avoid aliasing, and provide a clean low-jitter clock to the CLK pin to preserve aperture timing accuracy. Decoupling the supplies locally with 100 nF and 10 uF capacitors close to the AVDD and DVDD pins is recommended. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes drawn from the manufacturer datasheet, providing engineering context not available on the bare component listing.
HI5767/6CB-T - 10-Bit 60MSPS ADC | Renesas | 28-SOIC
The Renesas (formerly Intersil) HI5767/6CB-T is a monolithic 10-bit analog-to-digital converter fabricated in a CMOS process, sampling at 60 MSPS with an internal band-gap voltage reference. Housed in a 28-pin SOIC package, the device integrates a fully differential pipelined architecture, an internal sample-and-hold, and an internal voltage reference, enabling high-speed signal acquisition with minimal external components. Key specifications include a 10-bit resolution, 60 MSPS maximum sample rate, and 5 V single-supply operation. The pipelined architecture and 28-SOIC footprint make the device suitable for compact designs that demand wide bandwidth and low power consumption. The CMOS fabrication process ensures that the ADC delivers high-speed conversion while maintaining the low-power characteristics essential for embedded systems. The pipelined architecture uses multiple low-resolution stages, each feeding a flash sub-ADC, with digital error correction to achieve the 10-bit linearity specification. An internal band-gap voltage reference eliminates the need for an external precision reference, simplifying the analog front-end and reducing board space. The fully differential input structure provides excellent common-mode noise rejection for noisy digital environments. According to the manufacturer datasheet, the device is designed for high-speed applications where wide bandwidth and low power consumption are essential. Typical applications include digital video processing, IF sampling in communications receivers, CCD imaging systems, medical imaging front-ends, radar signal processing, and high-speed data acquisition cards. The internal reference and sample-and-hold make it particularly suited for cost-sensitive designs requiring single-supply operation. When designing with this part, attention must be paid to the input common-mode voltage range and the analog input bandwidth. Proper PCB layout with a clean analog ground plane and decoupling capacitors placed close to the supply pins is critical for achieving datasheet SFDR and SNR performance at 60 MSPS operation. This page synthesizes distributor pricing, drop-in alternatives within the HI5767 family, and practical design notes not found in the manufacturer datasheet alone.
HI5767/6IB - 10-Bit 60MSPS Pipelined ADC | Intersil | 28-SOIC
The Intersil (Renesas) HI5767/6IB is a 10-bit, monolithic, pipelined analog-to-digital converter (ADC) sampling at up to 60 MSPS, housed in a 28-pin SOIC wide-body package. The /6 speed grade variant supports 60 MSPS conversion rates and includes an internal 2.5 V bandgap voltage reference, providing a complete single-chip data-acquisition front-end for cost-sensitive designs. An ADC (Analog-to-Digital Converter) is a data-converter integrated circuit that samples continuous analog signals and outputs discrete digital codes. Pipelined ADCs use a multi-stage sub-ADC architecture to achieve high sampling rates (>10 MSPS) while keeping per-stage comparator counts low; they sit in the hierarchy of data-converter -> ADC -> pipelined ADC -> monolithic CMOS ADC -> mixed-signal IC. Pipelined ADCs are widely used in communications, imaging, and instrumentation where megahertz bandwidths must be digitized at moderate (8-14 bit) resolution. Key features of the HI5767/6IB include a single 5 V analog supply (3.3 V optional), single-ended analog input, internal voltage reference, low power consumption of approximately 175 mW at 60 MSPS, and TTL/CMOS-compatible digital outputs. The pipelined core is fabricated in a CMOS process and includes a built-in sample-and-hold, ensuring full Nyquist-bandwidth analog input capture without external front-end components. Architecturally, the HI5767/6IB combines a flash-style front-end quantizer with subsequent residue-gain stages in a digital-error-correction pipeline, achieving 10-bit linearity without laser trimming. The /6 grade variant is the fastest member of the HI5767 family, which also includes /4 (40 MSPS) and /2 (20 MSPS) grades sharing the same pinout. Designers can drop in a slower grade for lower-power applications without any PCB changes. Typical applications include set-top box video digitizers, digital oscilloscope front-ends, IF-sampling communications receivers, CCD/CIS image sensor digitizers, and ultrasound beam-former preprocessing. The 28-SOIC wide-body footprint provides strong thermal dissipation for continuous 60 MSPS operation and is friendly to hand-soldered prototypes and high-density mixed-signal boards. When designing with this device, place a 0.1 uF decoupling capacitor adjacent to each supply pin and keep analog/digital ground returns separated to a single point beneath the package. For applications requiring sampling above 40 MSPS, ensure the analog input source can drive the 50 ohm-equivalent input with adequate bandwidth, since the input is a switched-capacitor topology. This page synthesizes Renesas/Intersil datasheet specifications, current distributor stock and pricing, drop-in alternatives from the same HI5767 family, and practical layout notes not found in the standalone manufacturer datasheet.
HI5805BIB - 12-Bit 5MSPS Pipelined ADC | Renesas | 28-SOIC
The Renesas (formerly Intersil) HI5805BIB is a 12-bit, 5 MSPS pipelined analog-to-digital converter fabricated in Intersil's HBC10 BiCMOS process, housed in a 28-pin SOIC wide-body package. It delivers a single 1-input conversion channel with 5 megasamples-per-second throughput, targeting high-speed, high-resolution data-acquisition applications where wide bandwidth and low power consumption are essential. A pipelined ADC (analog-to-digital converter) is a successive-approximation architecture variant optimized for sampling rates from a few MSPS to hundreds of MSPS while keeping die area modest compared with flash converters. Pipelined ADCs sit within the broader signal-chain taxonomy of successive-approximation-register (SAR), delta-sigma, and flash ADCs, and they are widely used in digitizing IF, video, and instrumentation signals in the 1-100 MHz input bandwidth range. The HI5805 belongs to the data-acquisition IC family, which itself rolls up into the broader converter/mixed-signal/power-management hierarchy used by system architects. Key features include 5 MSPS guaranteed sampling rate, 12-bit resolution with no missing codes, single +5 V analog supply operation, and a single-ended analog input with internal reference buffer. The BiCMOS process allows the analog front-end to maintain low input-referred noise while the CMOS digital logic keeps standby power low. A wide-body 28-SOIC footprint gives the chip sufficient copper area to dissipate the conversion-stage power without an additional heatsink at room temperature. From an architectural standpoint, the HI5805 uses a multi-stage pipeline with inter-stage sample-and-hold residue amplifiers and an internal clock derived from an external CMOS clock. The parallel output data interface presents all 12 bits simultaneously, simplifying glue logic to an FPGA or ASIC. The device accepts a single-ended analog input within the input common-mode range of the internal track-and-hold amplifier. Typical applications include CCD imaging digitizers, baseband IF sampling in software-defined radio, ultrasound front-ends, transient capture on digital oscilloscopes, and medical imaging preprocessing. The 5 MSPS rate suits NTSC/PAL video-rate digitizers, while the 12-bit resolution satisfies CCD sensor quantization requirements. Industrial test equipment uses this converter when sub-MHz analog bandwidth signals need to be captured without aliasing. When laying out the PCB, keep analog input traces short and guarded by a ground pour to limit kickback noise from the internal T/H switches. Place a 0.1 uF ceramic bypass capacitor directly on the AVDD pin and a 10 uF bulk tantalum capacitor within 1 cm of the supply pin. Use a single ground plane if the digital return currents are kept on the opposite side of the board from the analog input. This page synthesizes distributor stock, drop-in alternative pinouts, and practical design notes not found in the original Renesas datasheet, giving engineers a single-source comparison reference for sourcing and second-source decisions.
HI5805BIBZ - 12-Bit 5MSPS ADC, Pipelined, 28-SOIC | Renesas
The Renesas HI5805BIBZ is a monolithic 12-bit, 5 MSPS analog-to-digital converter fabricated in Intersil's HBC10 BiCMOS process, packaged in a 28-pin SOIC (300 mil) with industrial temperature grade. It combines wide-bandwidth track-and-hold input, an internal 2.5 V reference, and a pipelined architecture for high-speed, high-resolution conversion in a single-ended analog input topology. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes. Pipelined ADCs use multiple cascaded low-resolution stages with inter-stage residue amplifiers and digital correction to reach high sample rates while keeping power dissipation moderate. The HI5805BIBZ sits at the lower end of the mid-speed pipelined family, intended for video-rate signal acquisition rather than oscilloscope-class streaming. Within the broader product hierarchy, it is part of Renesas's mixed-signal data-converter IC family, which also includes successive-approximation (SAR), sigma-delta, and flash converters. Key features include 5 MSPS throughput, 12-bit resolution, one single-ended input channel, a 0 to +5 LSB reference-error trim (per the Mouser part description), and an internal reference. The pipelined core typically yields 10 to 11 ENOB at full speed with an analog input range of 0 V to 2 V (or 2 Vp-p differential, datasheet-dependent). Operating on a single 5 V supply with low CMOS power, it dissipates roughly 80 mW typical at 5 MSPS. Architecturally, the HBC10 BiCMOS process allows combining low-noise bipolar analog front-ends with CMOS digital logic on the same die, which is what gives the HI5805BIBZ its wide analog bandwidth and low distortion while keeping digital control logic efficient. The track-and-hold front-end supports Nyquist-rate sampling of fast input signals, and the digital error-correction logic recovers the missing codes that raw pipelined stages would otherwise drop. Typical applications include professional video digitisation, CCD/camera sensor signal processing, baseband I/Q sampling for software-defined radio, industrial data-acquisition front-ends, and medical imaging input stages. The wide input bandwidth also suits transient-capture front-ends in test-and-measurement equipment. When designing with this part, decouple AVDD and DVDD with separate 0.1 uF and 10 uF ceramic capacitors placed as close as possible to each supply pin, and keep the analog input traces short and impedance-controlled to avoid degrading in SNR. A ground plane is required; do not route digital signals under the analog front-end. This page synthesizes distributor stock, Renesas drop-in alternatives, and practical PCB layout notes not found in the manufacturer datasheet.
HI5812JIB - 12-Bit 20us SAR ADC with T/H | Renesas
The Renesas HI5812JIB is a 12-bit, 20-microsecond successive-approximation-register (SAR) analog-to-digital converter with an internal track-and-hold, packaged in a 24-pin SOIC (300 mil). It operates from a single 3V to 6V supply and typically draws 1.9 mA, making it a low-power CMOS sampling ADC suitable for portable, industrial, and process-control data-acquisition front-ends. The part provides one input channel, an external clock or internal oscillator option, and a parallel digital interface for direct connection to microcontrollers and microprocessors. An ADC (analog-to-digital converter) is an integrated circuit that converts a continuous analog voltage into a discrete digital code. Within the data-converter hierarchy, the HI5812JIB belongs to the SAR sub-family, which performs one conversion in N successive approximation steps using a single comparator and a switched-capacitor DAC. SAR ADCs are valued for their deterministic latency, low power consumption, and inherent sample-hold behavior, making them ideal for multiplexed multi-channel systems and DC as well as audio-bandwidth signals up to tens of kHz. Key features of the HI5812JIB include 12-bit resolution with no missing codes, internal track-and-hold, single +3V to +6V supply operation, low 1.9 mA typical supply current, 20-microsecond typical conversion time, a parallel output bus, and three-state output buffers for direct bus interfacing. The 24-SOIC package is industry-standard and compatible with automated surface-mount assembly, easing manufacturing integration. Architecturally, the HI5812JIB combines a high-impedance CMOS input stage, a charge-redistribution DAC array, a low-noise comparator, and a SAR control logic block. The internal track-and-hold eliminates the need for an external sample-and-hold amplifier in most applications and defines a 2 MHz full-power bandwidth. The part supports both unipolar (0-VREF to VREF) and bipolar (-VREF to VREF) input ranges when VREF is tied to a clean reference such as 2.5V or 5V. Typical applications include process control and industrial automation data-acquisition boards, portable and battery-powered instrumentation, multiplexed data-logging systems, and digital signal-processor front-ends. Designers value the HI5812JIB for its small footprint, single-supply operation, and predictable SAR behavior in real-time control loops. When designing with this ADC, place a 0.1 uF decoupling capacitor as close as possible to the VDD pin and ensure a low-impedance ground return to preserve linearity. Drive the analog input with a low-output-impedance buffer because the internal T/H settling time directly limits acquisition accuracy at high source impedances. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the standalone manufacturer datasheet, giving engineers a single source for sourcing, substitution, and design guidance.
HI5812JIBZ - 12-Bit 50kSPS SAR ADC w/ Track & Hold | Renesas
The Renesas (formerly Intersil) HI5812JIBZ is a 12-bit, 50 kSPS successive-approximation-register (SAR) analog-to-digital converter with an internal track-and-hold amplifier, housed in a 24-pin wide-body SOIC package. The part operates from a single +5 V analog supply and provides a parallel 12-bit, 8-bit (MSBs), and 4-bit (LSBs) three-state CMOS output bus that latches across one full conversion cycle. Its single 0 V to VREF unipolar analog input accepts a 1.5 LSB maximum integral linearity error over the operating range. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a precision data-conversion architecture that uses a binary-search algorithm against an internal precision DAC to digitize an input voltage. SAR ADCs sit in the data-converter hierarchy between flash converters (fastest, lowest resolution) and sigma-delta converters (highest resolution, lowest speed). They deliver an excellent balance of speed, resolution, and power consumption for industrial, instrumentation, and process-control signal chains, and they guarantee no pipeline latency - a single conversion yields a complete 12-bit code. Key features of the HI5812JIBZ include a 20-microsecond typical conversion time, 50 kSPS guaranteed throughput, an on-chip clock oscillator, and a hardware CONVERT_START input plus a DATA_READY flag to simplify handshake with microcontrollers and microprocessors. The high-impedance analog input is sample-and-held internally, removing the need for an external buffer on moderate source-impedance signals. The 24-SOIC wide-body footprint gives generous thermal headroom and simplifies hand-soldering during prototype rework. The HI5812JIBZ is fabricated on a high-speed CMOS process with a precision thin-film ladder DAC. Its architecture ensures monotonic conversion and stable gain/offset over temperature, while the wide 24-SOIC package simplifies thermal management and PCB layout. Compared with discrete ADC + op-amp front ends, the integrated track-and-hold eliminates a full S/H stage BOM and reduces propagation uncertainty in multiplexed-channel systems. Typical applications include industrial process-control signal acquisition, multi-channel data-logging front ends, portable and battery-powered instrumentation, sonar/radar signal conditioning, and digital audio front-end monitoring. Designers frequently pair it with external reference ICs, anti-alias RC filters, and a 74HC574 latch or 8-bit microcontroller for bus de-multiplexing. When designing with this part, observe the recommended layout guidelines: keep analog and digital grounds separated and join them only at the AGND pin, decouple VDD and VREF with low-ESR ceramic capacitors placed within 5 mm of the supply pins, and provide a low-impedance reference such as the ADR01 or REF02 for full 12-bit absolute accuracy. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the original manufacturer datasheet and accelerate component selection.
HI5812JIBZ-T - 12-bit, 50kSPS SAR ADC | Renesas / Intersil
The Renesas / Intersil HI5812JIBZ-T is a 12-bit successive approximation register (SAR) analog-to-digital converter with an internal track-and-hold, sampling at up to 50 kSPS in a 24-pin SOIC wide-body (300 mil) package. Operating from a single 3 V to 6 V supply, the part typically draws 1.9 mA at 5 V and achieves a maximum conversion time of 20 microseconds at 5 V, making it suitable for medium-speed data acquisition front-ends where low power and tight loop latency matter. A SAR ADC (Successive Approximation Register analog-to-digital converter) is a type of data converter that resolves an analog input to its digital code through a binary-search algorithm executed by a precision DAC and comparator, one bit per clock cycle. SAR ADCs sit in the data-converter hierarchy between flash converters (faster, larger, more power-hungry) and sigma-delta converters (slower, higher resolution, with extensive digital filtering). They are favored where deterministic latency, no pipeline delay, and modest power consumption are all required - notably in industrial process control, instrumentation, and motor-control feedback loops. Key specifications include a parallel data interface for direct micro-processor or FPGA bus attachment, single-ended analog input architecture with built-in track-and-hold, and an operating temperature range of -40 C to +85 C suitable for industrial environments. The part is offered in a wide-body 24-SOIC outline (0.295 inch / 7.50 mm width), which eases PCB layout and provides robust lead-frame strength during automated assembly. Architecturally, the HI5812JIBZ-T combines a capacitive-charge redistribution DAC with a high-gain comparator and on-chip track-and-hold capacitor. The single 3 V to 6 V supply rail simplifies power-tree design versus bipolar +/- supplies and avoids the charge-pump noise that often appears on switched-capacitor inputs at low VDD. Typical applications include industrial process control data acquisition, portable instrumentation, closed-loop motor control position feedback, weigh-scale front ends, and multi-channel multiplexed data-acquisition systems where the ADC sits behind an external MUX. The combination of 50 kSPS throughput and 20 us conversion time is well matched to 50 Hz / 60 Hz power-line-conditioned industrial signals. When designing with this device, decouple VDD with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin and add a 10 uF bulk capacitor on the same node. Keep analog and digital grounds connected at a single point under the IC to limit switching noise coupling into the analog input. The internal track-and-hold front-end removes the need for an external buffer when source impedance stays below the value specified in the manufacturer datasheet. This page synthesizes distributor pricing as of 2026-10-13, verified drop-in alternatives, and practical layout guidance not aggregated on any single manufacturer or distributor page.
HI5812JIP - 12-Bit SAR ADC, 24-PDIP, Single 3-6V | Renesas
The Renesas (formerly Harris / Intersil) HI5812JIP is a 12-bit successive-approximation analog-to-digital converter (SAR ADC) with internal track-and-hold, packaged in a 24-pin PDIP (plastic DIP, 600 mil). It operates from a single 3 V to 6 V supply and typically draws just 1.9 mA when operating at 5 V, completing one conversion in approximately 20 microseconds for a ~50 kSPS throughput. The CMOS process keeps the part small and low-power for embedded and process-control front ends. The HI5812JIP accepts a unipolar analog input and provides a parallel digital output, simplifying interface to microcontrollers, FPGAs, and DSPs without needing an external serial-to-parallel stage. An on-chip track-and-hold captures fast-changing inputs accurately. The wide single-supply range (3 V to 6 V) lets the same part power from 3.3 V or 5 V rails. The 24-PDIP package is a through-hole, easy-to-socket package, making it convenient for prototyping, education, legacy upgrades and industrial control front-ends where socketed replacement is valued. The internal track-and-hold provides a true sample/hold path so that full-scale inputs near Nyquist can be digitized without an external buffer. The HI5812JIP is often used in audio digitization, process-control analog front-ends, instrumentation and as a learning vehicle for SAR architectures. The successive-approximation core trades pure speed for very low power, with no pipeline latency - a conversion result is fully settled and read on the same bus cycle. Operating temperature is typically 0 °C to +70 °C (J-grade commercial) - JIP suffix indicates the industrial/plastic DIP, non-automotive temperature grade, making it best suited for commercial and laboratory systems rather than harsh-environment automotive deployment. A decoupling capacitor close to VDD and a clean analog input reference are required for full 12-bit accuracy.
HI5812KIB - 12-Bit 20µs SAR ADC, 24-SOIC | Renesas/Intersil
The Renesas/Intersil HI5812KIB is a CMOS, 12-bit, successive-approximation analog-to-digital converter (SAR ADC) with an internal track-and-hold, capable of completing a full conversion in approximately 20 microseconds. Housed in a 24-pin SOIC wide-body package, the device operates from a single 3V to 6V supply and typically draws just 1.9mA while converting, making it suitable for low-power instrumentation. A successive-approximation ADC is a type of data converter that uses a binary-search algorithm against an internal precision DAC to digitize an analog input one bit at a time per clock cycle. Within the broader hierarchy, the HI5812KIB belongs to the SAR ADC family, which in turn sits under the ADC/DAC converter category, the data-converter IC class, and ultimately the integrated circuit (semiconductor) hierarchy. SAR converters are valued for their deterministic latency, fixed acquisition time, and excellent DC accuracy, which is why they dominate precision measurement, industrial control, and data-acquisition front ends. The HI5812KIB integrates a sample-and-hold amplifier on-chip, removing the need for an external track-and-hold component. Its 12 high-speed CMOS three-state data outputs are latched and held throughout the full conversion cycle, and the output is user-selectable as 12-bit, 8-bit (MSBs), or 4-bit (LSBs) word widths. A data-ready flag and a conversion-start input complete the digital interface, allowing straightforward connection to microcontrollers, DSPs, or asynchronous parallel buses. Typical applications include process control and industrial data-acquisition front ends, battery-powered portable instrumentation, precision sensor signal conditioning, and digital audio/video signal monitoring. The wide 3V–6V single-supply range and low 1.9mA supply current suit battery and field-bus powered systems where the ADC must share a rail with logic. The deterministic 20 µs conversion time is well matched to closed-loop control loops operating at sub-50kHz sampling rates, including weigh scales, panel meters, and multi-channel scanner systems. When designing with the HI5812KIB, ensure the analog input drive impedance is below the value recommended in the manufacturer datasheet so that the internal acquisition capacitor settles within the allotted aperture window. Decouple VDD with a low-ESR 0.1µF ceramic capacitor placed within 5mm of the supply pin and add a 10µF bulk tantalum capacitor at the board entry point. This page synthesizes distributor pricing, verified drop-in alternatives in the 24-SOIC footprint, and design considerations beyond the manufacturer datasheet to support component selection and PCB redesign decisions.
HI5812KIBZ - 12-Bit SAR ADC, 50ksps, 24-SOIC | Renesas
The Renesas Electronics HI5812KIBZ is a 12-bit successive approximation register (SAR) analog-to-digital converter with internal track-and-hold, packaged in a 24-pin SOIC (0.295 inch, 7.50 mm width). It operates from a single 3 V to 6 V supply, draws a typical supply current of 1.9 mA, and supports a maximum sampling rate of 50 ksps with single-ended analog input. A SAR ADC (successive-approximation-register analog-to-digital converter) is a type of data converter that resolves a single bit per clock cycle using a binary search against a precision DAC. SAR ADCs sit in the broader converter hierarchy alongside flash, pipeline, sigma-delta, and dual-slope architectures. The SAR topology is favored where low latency, deterministic conversion time, moderate resolution (8-16 bit), and small package size are required, making it the workhorse choice for industrial control, instrumentation, and data acquisition front ends. The HI5812KIBZ features 20-microsecond conversion time (50 ksps throughput), a built-in sample-and-hold, single +5 V operation, and an industry-standard 24-SOIC outline for ease of layout. Combined with CMOS low power consumption (1.9 mA typical IDD), this ADC targets embedded data acquisition where board space and battery life are at a premium. Internal calibration-free operation removes the start-up complexity found in some competing parts. The device implements a classic charge-redistribution SAR core with a laser-trimmed thin-film resistor ladder for the DAC. An internal track-and-hold captures the input within the acquisition window, then holds the value constant during the 12-bit successive-approximation cycle, removing the need for an external high-bandwidth amplifier. The digital interface is a parallel 12-bit output bus with standard CS and RD control signals. Typical applications for the HI5812KIBZ include industrial process control loops, portable battery-powered instrumentation, multi-channel data acquisition boards, and precision sensor signal conditioning where 12-bit resolution is sufficient. It is well-matched to 4-20 mA loop receivers, strain-gauge bridges, and thermocouple digitizers. When designing with this device, follow the datasheet reference layout with a 0.1 uF ceramic decoupling capacitor placed within 5 mm of the AVDD pin and an additional 10 uF bulk capacitor on the supply rail. Source impedance should be kept below 1 kohm to preserve acquisition accuracy, and digital traces must be kept away from the analog input to minimize digital-coupling noise. This page synthesizes distributor pricing from authorized channels, lists 5 verified drop-in 24-SOIC alternatives, and provides practical design notes beyond what the manufacturer datasheet alone offers.
HI7191IB - 24-Bit Sigma-Delta ADC, 20-SOIC | Renesas Electronics
The Renesas HI7191IB is a 24-bit, high-precision, monolithic instrumentation sigma-delta analog-to-digital converter (ADC) that operates from ±5V supplies and is housed in a 20-pin SOIC (Wide) package. It delivers fully differential signal and reference inputs, an internal Programmable Gain Instrumentation Amplifier (PGIA) with gains from 1 to 128, and an on-demand converter that auto-calibrates on demand. The serial I/O port is compatible with both Motorola 6805/11 SPI and Intel 8051 SSR synchronous formats. A sigma-delta (Σ-Δ) ADC is a type of analog-to-digital converter that oversamples the input signal and uses noise shaping to push quantization noise out of the baseband. Within the broader taxonomy, sigma-delta ADCs sit under successive-approximation and integrating ADCs as part of the data-converter family, which in turn belongs to the data acquisition IC category and ultimately to the broader power and signal-chain semiconductor hierarchy. They are the preferred architecture for precision DC measurement applications where high effective resolution and excellent linearity outweigh the need for high absolute sampling rates. Key features of the HI7191IB include 24-bit resolution, internal digital calibration, an on-chip PGIA providing 1x to 128x input gain, and flexible serial communication. The PGIA eliminates the need for external pre-amplifiers in most applications, simplifying front-end design and reducing board area. The on-demand calibration mechanism removes offset and gain errors at any time, including immediately after power-up or after operating-condition changes, ensuring repeatable conversion accuracy across production units. The HI7191IB architecture uses a switched-capacitor modulator followed by a digital decimation filter, with separate calibration registers that the user can read and write. This decoupled modulator/filter design allows the user to trade off output word rate against effective noise-free resolution, while the calibration registers give the system designer visibility into error sources. The serial interface supports both SPI and SSR protocols, enabling direct connection to most microcontrollers and DSPs without external glue logic. Typical applications for the HI7191IB include industrial weigh scales, pressure and strain-gauge transducer readouts, precision temperature measurement with thermocouple or RTD front-ends, process-control instrumentation, and portable analytical instruments such as blood-glucose meters and multi-meters. It is also widely used in the field of smart sensors and 4-20 mA loop-powered transmitters that require a wide dynamic range and low-noise conversion of small differential sensor outputs. When integrating the HI7191IB into a multi-channel system, the serial-interface architecture lets multiple parts share the same bus with individual chip-select lines. Designers should pay attention to the analog supply bypassing on both the +5V and -5V rails, as the sigma-delta modulator is sensitive to high-frequency supply noise; place 10 uF tantalum and 0.1 uF ceramic capacitors as close to the supply pins as possible, with the 0.1 uF capacitor leading to a low-impedance ground plane. Common-mode input voltage range and reference voltage range must both stay within the supply rails to avoid linearity degradation at the converter's full-scale output. This page synthesizes distributor pricing, drop-in SOIC-20 alternatives, and practical design notes for the HI7191IB that go beyond what is found in the manufacturer datasheet.
HI7191IBZ - 24-Bit Sigma-Delta ADC | ±5V 20-SOIC | Renesas
The Renesas (formerly Intersil) HI7191IBZ is a 24-bit, high-precision, sigma-delta analog-to-digital converter that operates from ±5V dual supplies in a 20-pin SOIC wide-body package. It integrates a monolithic instrumentation-grade front-end with a sigma-delta modulator and digital filter, delivering one differential input channel at up to 2 kSPS conversion rate with fully differential signal and reference inputs. A sigma-delta (Σ-Δ) analog-to-digital converter is a precision converter architecture that oversamples the input signal at a much higher frequency than the target output rate and uses noise shaping to push quantization noise out of the baseband. The Σ-Δ family sits within the broader hierarchy of analog-to-digital converters -> data converters -> signal chain ICs -> mixed-signal semiconductors, and is the dominant topology for high-resolution (>20-bit), low-bandwidth precision measurement applications such as weigh scales, strain gauges, thermocouples, and industrial instrumentation front-ends. Key features include an internal programmable-gain instrumentation amplifier (PGIA) providing gains from 1 to 128 to eliminate external pre-amplifiers, on-demand auto-calibration of the line-to-ground and reference paths, and 24-bit noise-free resolution. Both the analog signal inputs and the reference input are fully differential, maximizing common-mode rejection for sensor-bridge and ratiometric measurement topologies. Architecturally, the device combines a chopper-stabilized instrumentation amplifier, a second-order sigma-delta modulator, and a digital decimation filter. Calibration registers compensate for offset and gain errors, allowing system designers to achieve better than 20-bit effective resolution in real measurement channels. The ±5V supply requirement supports high common-mode input ranges, which is essential when interfacing directly to bridge-type sensors in industrial environments. Typical applications include precision weigh scales, industrial process-control analog front-ends, strain-gauge and load-cell signal chains, and laboratory instrumentation. The on-demand calibration feature is particularly valuable for systems that must retain accuracy across long unattended operation. When designing with this part, allocate adequate decoupling at each V+ and V- pin (typically 10 µF tantalum in parallel with 0.1 µF ceramic) and follow a star-ground layout for the analog ground return, because residual common-mode disturbance on the reference directly translates into gain error. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
HI7191IBZ-T - 24-Bit Sigma-Delta ADC, SOIC-20 | Renesas
The Renesas (formerly Intersil) HI7191IBZ-T is a monolithic 24-bit instrumentation-grade sigma-delta analog-to-digital converter that operates from ±5 V supplies and integrates a programmable-gain instrumentation amplifier (PGIA) with gains from 1 to 128. It is offered in a 20-pin SOIC (SOIC-20 / MS-013-AC) industrial-temperature package with a 5 V single/dual supply rail and fully differential signal and reference inputs. A sigma-delta ADC is a type of oversampling converter that trades raw speed for very high resolution by pushing quantization noise to high frequencies where it can be digitally filtered away; the technique is widely used in precision measurement, weigh scales, sensor front-ends, and industrial instrumentation where DC accuracy and noise rejection matter more than bandwidth. The HI7191 belongs to the broader hierarchy of mixed-signal data converters (ADC -> sigma-delta ADC -> precision ADC -> data converter IC), and within Renesas it sits in the legacy Intersil precision-converter family. Key features highlighted in the manufacturer datasheet include 24-bit no-missing-code resolution, integrated PGIA with gains of 1, 2, 4, 8, 16, 32, 64, and 128 eliminating the need for an external pre-amplifier, fully differential analog inputs, an on-demand converter that auto-calibrates on power-up, and a serial interface for digital readback. Industrial operating temperature range of -40 °C to +85 °C makes it suitable for factory-floor and process-control environments. Typical applications span weigh scales, load-cell bridges, strain-gauge signal chains, temperature-bridge measurements (RTD and thermocouple front-ends with PGA), industrial pressure transmitters, and multi-channel data-acquisition front-ends where the PGIA directly digitizes the conditioned bridge output. The integrated PGIA is the main architectural differentiator versus competing 24-bit ADCs that require a separate external instrumentation amplifier. When designing with the HI7191IBZ-T, observe the supply-rail and reference-decoupling guidance from the datasheet, place the analog/digital grounds on a common star, and route the serial interface traces away from the analog inputs to preserve CMRR. Renesas marks this part Obsolete on the product family page, so engineers designing new boards should confirm longevity of supply or evaluate pin-compatible drop-in alternatives listed below.
HI7191IPZ - 24-Bit Sigma-Delta ADC, ±5V, 20-PDIP | Renesas
The Renesas (formerly Intersil) HI7191IPZ is a 24-bit, high-precision instrumentation sigma-delta analog-to-digital converter that operates from ±5V analog and digital supplies and is housed in a 20-pin PDIP (plastic DIP) through-hole package. The device integrates a fully differential signal input path, a fully differential reference input, and an on-chip programmable-gain instrumentation amplifier (PGIA) with binary gain steps from 1 to 128, eliminating the need for an external pre-amplifier in most transducer front-ends. The serial I/O port is compatible with both Motorola 6805/11-series SPI and Intel 8051-series SSR synchronous transfer formats. An ADC of the sigma-delta type is a noise-shaping converter that oversamples the input at a rate far above the Nyquist frequency and pushes quantization noise out of the baseband, trading speed for resolution. The HI7191IPZ is part of the instrumentation ADC category, which sits hierarchically inside precision data converters, alongside successive-approximation (SAR) ADCs at lower resolution and wider bandwidth. Compared with successive-approximation ADCs, instrumentation sigma-delta converters such as the HI7191IPZ deliver far higher effective resolution at low word rates while integrating input conditioning, making them ideal for direct connection to bridge sensors, thermocouples, and other low-level differential sources. Key differentiating features include 24-bit resolution, the on-chip PGIA with gains of 1, 2, 4, 8, 16, 32, 64, and 128, on-chip calibration registers that allow user-initiated self- and system-calibration routines, and a low-power standby mode controlled through the serial interface. The combination of differential inputs, a differential reference, and integrated gain front-end allows the converter to maintain high common-mode rejection and resolution over the full-scale input range. The converter architecture combines a charge-balancing modulator, a digital decimation filter, and the integrated PGIA, yielding a single-chip instrumentation front-end. The HI7191IPZ targets a maximum output word rate of approximately 2 kSPS at full 24-bit resolution, making it suited to DC and quasi-DC precision measurements rather than wideband signal acquisition. The HI7191IPZ is pin-compatible with the HI7190IPZ, which shares the same die but offers tighter linearity specifications for the most demanding calibration channels. Typical applications include precision weighing scales and load-cell readouts, industrial process-control pressure and strain instrumentation, laboratory and analytical instrumentation such as pH and conductivity meters, thermocouple and RTD temperature acquisition modules, and battery-powered portable instrumentation where the standby mode and low input current draw help extend operating life. Designers most often place the HI7191IPZ between the transducer bridge and an external microcontroller, with the MCU configuring PGIA gain, calibration, and channel selection via the four-wire synchronous serial interface. Key design considerations include providing well-decoupled analog and digital ±5V supplies, buffering inputs where source impedance is high, and writing a calibration routine that exercises the on-chip zero-scale and full-scale registers. Note that the HI7191IPZ is currently listed as obsolete on the Renesas product page, so designers should confirm long-term availability or plan around the pin-compatible HI7190IPZ. This page synthesizes distributor pricing, package information, parametric comparison data, and pin-compatible alternatives not aggregated on any single distributor page.
HI9P5701K-5 - 6-Bit 30MSPS Flash ADC, 18-SOIC | Renesas
The Renesas HI9P5701K-5 is a monolithic 6-bit CMOS flash analog-to-digital converter sampling at 30 MSPS in an 18-pin SOIC wide-body package, with a single +5V analog supply and TTL/CMOS-compatible digital outputs. The flash architecture uses 63 parallel comparators to deliver a full 6-bit conversion in a single clock cycle, enabling sub-100 ns latency suitable for digital oscilloscope front-ends, video digitizers, and radar IF signal capture. A flash ADC is the fastest ADC architecture available, performing quantization in one step using a bank of comparators and a resistor ladder, in contrast to successive-approximation (SAR) converters that resolve one bit per clock cycle. Flash ADCs trade resolution for speed, making them ideal for sub-8-bit high-bandwidth applications where latency must be near zero. The HI9P5701K-5 occupies the lower-resolution tier of the flash family, sitting beneath 8-bit and 10-bit flash parts and competing with high-speed pipeline ADCs only when absolute lowest latency is required. Key specifications include 30 MSPS minimum sampling rate, 6-bit parallel output, single +5V supply operation, and CMOS/TTL-compatible digital outputs. The 18-SOIC wide-body (7.5 mm) package offers a familiar through-hole-replacement footprint for prototyping while still supporting surface-mount assembly. The internal architecture combines a precision resistor ladder, 63 latched comparators, and a priority encoder to produce a binary output word, with an overflow bit for out-of-range indication. The 30 MSPS analog input bandwidth allows the HI9P5701K-5 to digitize signals with frequency content up to approximately 15 MHz (per Nyquist), making it well suited to baseband and low-IF applications. Designers can also operate the part at lower sample rates for reduced power dissipation, though the flash architecture does not offer the dynamic scaling of pipeline or SAR converters. Typical applications include digital oscilloscope front-ends, video digitizers and frame grabbers, ultrasound medical imaging receive channels, radar IF digitizers, and digital communication test equipment. The 18-SOIC wide-body package simplifies hand prototyping while remaining suitable for high-volume SMT assembly. When designing with the HI9P5701K-5, ensure the analog input is bandwidth-limited to less than 15 MHz to prevent aliasing, and place a high-quality sample-and-hold or anti-aliasing filter directly at the input pin. The wide-body SOIC requires a 7.5 mm land pattern - do not substitute a narrow-body SOIC footprint. Decouple VDD with a 100 nF ceramic placed within 5 mm of the supply pin. This page synthesizes distributor stock and pricing, drop-in 18-SOIC wide-body alternatives, and practical layout notes not consolidated in the original Renesas / Intersil datasheet, giving procurement and design engineers a single source for cross-reference and lifecycle decisions.