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EPM9560RC240-20C - MAX 9000 CPLD 560 Macro 240-RQFP | Altera
EPM9560RC240-20C

EPM9560RC240-20C - MAX 9000 CPLD 560 Macro 240-RQFP | Altera

The Altera EPM9560RC240-20C is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 216 maximum user I/O pins in a 240-pin RQFP package, operating from a 5.0 V supply with a 20 ns pin-to-pin propagation delay. It is a high-performance CMOS EEPROM-based programmable logic device built on Altera's third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on characteristics of a PAL. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. The MAX 9000 family uses EEPROM configuration cells, so the EPM9560RC240-20C retains its configuration without an external boot PROM and is live within microseconds of power-up. Key features include 560 macrocells organized into 35 logic array blocks (LABs), 12,000 usable gates, 216 maximum user I/O pins, a 20 ns pin-to-pin propagation delay (tPD1), and a 144 MHz internal counter frequency (fCNT). The device supports 5.0 V in-system programmability (ISP) and is specified for 0 C to 70 C commercial operation. The MAX 9000 architecture routes signals through a programmable interconnect array that feeds 35 LABs, each containing 16 macrocells with individual product-term allocation. This architecture delivers deterministic, predictable timing - a critical advantage over SRAM-based FPGAs for glue-logic, bus-interface, and state-machine functions where worst-case delay must be guaranteed. Typical applications include PCI and ISA bus bridging, memory controller glue logic, industrial control state machines, telecommunications line-card logic, and legacy system replacement where 5 V logic levels and instant-on operation are required. When designing with the EPM9560RC240-20C, note that it is a 5.0 V-only device and is not 3.3 V tolerant on all pins; level shifting is required when interfacing to modern 3.3 V or 1.8 V logic. The 240-pin RQFP package requires careful thermal and signal-integrity planning at 144 MHz. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for replacement and redesign decisions.

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EPM9560RC240-20N - MAX 9000 CPLD 560 Macro 240-RQFP | Altera
EPM9560RC240-20N

EPM9560RC240-20N - MAX 9000 CPLD 560 Macro 240-RQFP | Altera

The Altera EPM9560RC240-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, and 216 maximum user I/O pins, housed in a 240-pin RQFP (PowerQuad/plastic quad flat pack) package. It operates from a 5.0 V supply with a 20 ns pin-to-pin propagation delay (tPD1) and a 144 MHz internal counter frequency. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL/PLD. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic device. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using CMOS EEPROM configuration cells that retain their programmed state without external configuration memory. Key features of the EPM9560RC240-20N include 560 macrocells organized into 35 logic array blocks (LABs), 12,000 usable gates, 216 user I/O pins, and 5.0 V in-system programmability (ISP). The EEPROM-based configuration provides instant-on operation, eliminating the boot delay and configuration PROM required by SRAM-based FPGAs. The 20 ns speed grade (-20) delivers 144 MHz counter performance and 3.0 ns flip-flop setup time (tSU). The MAX 9000 architecture uses a continuous interconnect array that provides deterministic, uniform pin-to-pin timing independent of routing, which simplifies static timing analysis compared with segmented FPGA routing. Each macrocell contains a programmable flip-flop with individual clock, clear, and preset control, allowing mixed sequential and combinatorial logic in a single device. Typical applications include glue logic consolidation, bus bridging and protocol conversion, address decoding, state machines, and legacy system replacement where 5.0 V logic levels and instant-on operation are required. The 240-pin RQFP package provides 216 I/O for wide bus interfaces. When designing with this device, note that the -20 speed grade is the slowest MAX 9000 grade; timing-critical paths should be verified against the 20 ns tPD1 and 3.0 ns tSU limits. The 5.0 V core also requires level shifting when interfacing with modern 3.3 V or 1.8 V logic. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and migration decisions.

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EPM9560RC240-3 - MAX 9000 CPLD 560 Macrocell | Altera
EPM9560RC240-3

EPM9560RC240-3 - MAX 9000 CPLD 560 Macrocell | Altera

The Altera EPM9560RC240-3 is a MAX 9000 series Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and a 3 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (PowerQuad II) package. It operates from a 5 V supply and provides 192 user I/O pins for high-density glue logic, bus interfacing, and state machine implementations. A CPLD (Complex Programmable Logic Device) is a programmable logic IC built from non-volatile EEPROM cells that retain configuration without external memory. Within the logic IC hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers fewer logic resources than an FPGA but delivers deterministic, single-cycle timing and instant-on operation. The MAX 9000 family extends this architecture to FPGA-like densities using multiple Logic Array Blocks (LABs) interconnected by a fast, predictable routing matrix. The EPM9560RC240-3 delivers 560 macrocells organized into 20 LABs, each containing 16 macrocells with individual product-term logic. Its 3 ns pin-to-pin delay (speed grade -3) supports synchronous interfaces up to approximately 150 MHz, while the 5 V core and I/O simplify direct interfacing to legacy TTL and CMOS buses without level shifters. The 240-pin RQFP package provides 192 I/O pins, enabling wide address/data bus decoding in a single device. Architecturally, the MAX 9000 uses EEPROM-based configuration, giving the device instant-on capability and high immunity to single-event upsets compared with SRAM-based FPGAs. The multi-LAB structure with a programmable interconnect array (PIA) provides deterministic routing delays, which simplifies static timing analysis for critical control paths. Typical applications include PCI and ISA bus bridging, telecommunications line-card control, industrial automation controllers, and legacy system glue logic where 5 V signaling and non-volatile configuration are required. The device is widely used as a replacement for discrete 74-series logic and older PAL devices in long-lifecycle industrial and telecom equipment. When designing with the EPM9560RC240-3, note that the 5 V core draws significant quiescent current and requires adequate decoupling on every VCC pin. Because the part is obsolete, designers should verify availability and consider pin-compatible MAX 9000 speed-grade variants or migration to modern CPLDs for new designs. This page synthesizes distributor availability, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for engineers maintaining or sourcing this legacy CPLD.

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EPM9560RC28-15 - MAX 9000 CPLD 560 Logic Elements 15ns 5V | Altera
EPM9560RC28-15

EPM9560RC28-15 - MAX 9000 CPLD 560 Logic Elements 15ns 5V | Altera

The Altera EPM9560RC28-15 is a member of the MAX 9000 family of high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on Altera's third-generation Multiple Array MatriX (MAX) architecture, housed in a 28-pin ceramic windowed DIP-style RC package. It integrates approximately 6,000 usable gates and 560 logic elements in a single in-system programmable device with a 15ns pin-to-pin propagation delay (tPD). The device supports 5.0V in-system programmability through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, enabling rapid prototyping and field upgrades without removing the part from the board. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that combines the deterministic timing of classic PLDs with higher logic density and interconnect flexibility. In the broader system hierarchy, a CPLD sits between a small FPGA and discrete TTL/CMOS glue logic, providing predictable propagation delays, instant-on behavior at power-up (no boot PROM required), and excellent pin-locking capability for multi-voltage I/O bridging. The MAX 9000 family is positioned as the high-density workhorse of the classic Altera MAX series, sitting above MAX 7000 and below early Cyclone FPGAs in capability. Key features of the EPM9560RC28-15 include 212 macrocells, 16 logic array blocks (LABs), a maximum of 212 user I/O pins in the largest package, and 5V tolerant I/O cells supporting both 3.3V and 5V interfaces via programmable drive strengths. The device also provides JTAG boundary-scan test capability conforming to IEEE 1149.1, four user-defined I/O banks for mixed-voltage designs, and global control signals with programmable inversion. The 15ns speed grade makes it suitable for control logic, bus decoding, and address decoding in legacy 5V systems. The MAX architecture uses a Logic Array Block (LAB) matrix with continuous interconnect channels (called the Programmable Interconnect Array, or PIA) and an I/O block architecture that supports registered, latched, or combinational I/O with programmable output enables. Each macrocell contains a programmable AND/OR array, a flip-flop, and a programmable clock/clear configuration, allowing designers to implement complex combinatorial and sequential logic in a deterministic fashion. The EEPROM-based configuration cell ensures instant-on behavior with no external boot device required. Typical applications include bus interface bridging, peripheral controller glue logic, address decoding and DMA control in industrial and telecom backplane designs, legacy 5V system logic replacement, automotive body electronics, and military/aerospace systems (the -15 speed grade and RC ceramic package indicate high-reliability / military temperature range). The EPM9560RC28-15 is also well-suited to ASIC prototyping, test equipment front-ends, and any system that requires deterministic 15ns timing with non-volatile configuration. When designing with this device, note that the RC-28 suffix indicates a 28-pin ceramic windowed DIP package with the speed grade -15. The window allows ultraviolet erasure of the EEPROM array for reuse during prototyping. Engineers should provide a clean 5V ±5% supply and follow Altera's MAX 9000 JTAG programming guidelines for in-system configuration. This part is mature; consult Altera's PDN archive for current lifecycle status before new designs. This page synthesizes verified distributor data, package-level pinout detail, drop-in alternatives from the MAX 9000 family, and practical design notes not found on the manufacturer datasheet summary page.

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EPM9560RC304-10 - MAX 9000 CPLD, 560 Logic Elements | Intel
EPM9560RC304-10

EPM9560RC304-10 - MAX 9000 CPLD, 560 Logic Elements | Intel

The Intel (Altera) EPM9560RC304-10 is a high-density CMOS erasable programmable logic device (EPLD) from the MAX 9000 family, packaged in a 304-pin RQFP (RC) carrier with 12 ns pin-to-pin propagation delay. It delivers 560 macrocells / 16,000 usable gates and operates from a 5 V supply with in-system programmability through JTAG. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital logic device that combines the deterministic timing of PAL/GAL architecture with the density of an FPGA. In the system hierarchy, the EPM9560RC304-10 sits at the complex programmable logic tier, above simple PLDs (PAL/GAL), below low-density FPGAs, and parallel to other MAX 9000 family members. It serves as glue logic, bus interface, and state-machine fabric in systems where deterministic 12 ns timing and instant-on non-volatile configuration are required. Key features include 304 user I/O pins, JTAG-compliant IEEE 1149.1 boundary-scan support, pin-compatible speed grades (-10, -12, -15, -20), 5 V tolerant I/O with 3.3 V PCI-compatible variants, and 100% stuck-fault coverage via JTAG. The MAX 9000 architecture uses a global interconnect matrix that delivers predictable, fixed propagation delays regardless of placement or routing, simplifying timing closure. The device employs a 0.65 µm CMOS EEPROM process with non-volatile configuration cells, allowing instant-on operation without external boot memory. Multiple Logic Array Blocks (LABs) of 16 macrocells each are stitched together through a programmable interconnect array (PIA), and each macrocell contains a programmable flip-flop with product-term or D flip-flop mode. Typical applications include bus-interface bridging in telecom backplanes, peripheral glue logic for PowerPC and Pentium-era processor systems, address decoding for ISA/PCI/VME buses, and high-performance state-machine controllers in industrial automation. The 560-macrocell density makes it well suited to replace multiple discrete PAL/GAL devices with a single footprint. When designing with the EPM9560RC304-10, observe the 5 V VCC tolerance window and ensure decoupling capacitors (0.1 µF plus 10 µF bulk) are placed within 5 mm of every VCC/GND pair. Boundary-scan testing through the JTAG pins is recommended for production test access. This page synthesizes distributor pricing, MAX 9000 family cross-reference, and design notes for the EPM9560RC304-10 that are not available in the original Altera MAX 9000 datasheet alone.

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EPM9560RC304-15 - 560-Macrocell MAX CPLD, 15ns | Altera / Intel
EPM9560RC304-15

EPM9560RC304-15 - 560-Macrocell MAX CPLD, 15ns | Altera / Intel

The Altera (now Intel Programmable Solutions Group) EPM9560RC304-15 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, integrating 560 macrocells in a 304-pin RQFP (plastic Quad Flat Pack) package with a 15 ns pin-to-pin propagation delay. The device is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which combines the fine-grained architecture of traditional PLDs with the high density of FPGAs in a single, in-system-programmable package. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays on a single chip with a programmable interconnect. CPLDs sit in the broader hierarchy: programmable logic -> programmable logic device -> CPLD -> MAX architecture -> non-volatile logic. Unlike SRAM-based FPGAs, the EPM9560RC304-15 retains its configuration in on-chip EEPROM and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, eliminating the need for a separate programmer and enabling field upgrades. Key features include 560 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, a 15 ns combinatorial propagation delay (tPD), and a maximum operating frequency that supports high-speed glue-logic and bus-interface applications. The 5.0-V tolerant I/O and PCI-compliant drive capability allow direct interfacing with 5-V TTL logic and PCI bus signals without external buffering. Typical applications include high-speed address decoding and bus arbitration, complex state-machine controllers, interface bridging between microprocessors and peripherals, and PCI bus target devices. Designers commonly pair the EPM9560RC304-15 with synchronous SRAM, microcontrollers, and DMA controllers in industrial automation, telecommunications, and embedded computing designs. When designing with this part, pay close attention to the I/O pin count (212 user I/Os across 304 pins leaves 92 pins for power, ground, JTAG, and dedicated inputs) and ensure proper decoupling on all VCCINT and VCCIO rails. Use the JTAG interface for both ISP and boundary-scan testing to streamline manufacturing test flow. This page synthesizes distributor inventory, drop-in alternative listings, and design notes not found in the original MAX 9000 datasheet to accelerate sourcing and board bring-up.

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EPM9560RC304-15 - MAX 9000 CPLD, 560 Cells, 304-RQFP | Intel
EPM9560RC30415

EPM9560RC304-15 - MAX 9000 CPLD, 560 Cells, 304-RQFP | Intel

The Intel EPM9560RC304-15 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 12,000 usable gates, 560 macro cells, and a 304-pin RQFP (Power Quad Flat Pack) package with 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. It is built on the third-generation Multiple Array MatriX (MAX) architecture, combining high logic density with predictable, fast interconnect delays suitable for high-speed control logic, bus interfacing, and glue-logic integration. The -15 speed grade corresponds to a 15 ns pin-to-pin delay (tpD), supporting internal clock frequencies up to approximately 117.6 MHz. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks with a central programmable interconnect matrix. In the system hierarchy, a CPLD sits between small SPLDs/GALs and large FPGAs, offering deterministic timing, instant-on behavior from on-chip EEPROM, and high I/O counts. CPLDs are commonly used for bus bridging, address decoding, power-sequencing logic, and state-machine control where deterministic propagation delay is critical. The EPM9560RC304-15 features 16 logic array blocks (LABs) of 40 macro cells each (560 total), 360 user I/O pins, four dedicated inputs, and pin-compatible migration paths across MAX 9000 densities. Per the MAX 9000 datasheet family, it operates from a 5.0 V VCCINT/VCCIO supply, supports JTAG boundary-scan testing, and includes built-in ISP through the JTAG port. The 304-RQFP package provides a robust, high-pin-count surface-mount footprint for industrial and telecom systems. Typical applications include 32-bit microprocessor peripheral glue logic, PCI bus interface bridges, telecom channelized control logic, industrial control and instrumentation, and high-pin-count state-machine controllers. The high-pin-count package can integrate multiple parallel buses into a single device, reducing overall system part count and PCB area. When designing with this device, ensure that 5.0 V I/O compatibility is maintained with the chosen MCU or ASIC, and verify timing margins against the 15 ns tpD requirement at worst-case commercial temperature. Programming requires a JTAG-compatible programmer and the MAX+PLUS II or Quartus legacy software toolchain. This page synthesizes distributor stock and pricing, drop-in alternatives within the MAX 9000 family, and practical design notes not always collected in the legacy datasheet, providing an aggregated engineering reference for the EPM9560RC304-15.

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EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C

EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera

The Altera EPM9560RC304-15C is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 12,000 usable gates, 560 macro cells, and a maximum operating frequency of 117.6 MHz in a 304-pin RQFP package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, the device supports in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, and operates from a single 5.0 V supply. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic IC that combines multiple PAL/GAL-style logic blocks on a single die, sitting in the broader taxonomy of programmable logic devices (PLD) -> logic ICs -> integrated circuits -> semiconductors. CPLDs are characterized by deterministic pin-to-pin propagation delay, in-system re-programmability, and high fan-in macro cells, making them ideal for glue logic, bus interfacing, and state-machine replacement in systems where an FPGA would be over-specified. Key features of the EPM9560RC304-15C include 560 macro cells distributed across 16 Logic Array Blocks (LABs), 35 ns maximum pin-to-pin combinatorial propagation delay (the "-15" speed grade), 212 user I/O pins, and 5 V tolerant inputs with programmable open-drain or 3-state outputs. The MAX 9000 family uses an enhanced EEPROM process that delivers 100 program/erase cycles minimum and supports the 5.0 V in-system programming standard defined by the IEEE 1149.1 boundary-scan interface. The architecture is built around four dedicated input pins, four global clock pins, and the Programmable Interconnect Array (PIA) that routes signals between LABs without contention. Each macro cell contains a programmable AND/OR array, a flip-flop, and configurable I/O control, supporting both registered and combinatorial logic with per-pin slew-rate control. The "C" suffix in the part number denotes the commercial operating temperature range (0 C to +70 C). Typical applications for the EPM9560RC304-15C include high-density bus interface bridging, peripheral controllers in telecom backplanes, industrial control state machines, and pin-compatible drop-in replacement of legacy 304-pin RQFP CPLDs. The combination of 212 user I/O and 560 macro cells makes it well suited to designs that aggregate multiple discrete 74-series logic devices into a single programmable part. When designing with this device, note that the -15 speed grade provides a maximum internal operating frequency of 117.6 MHz and a pin-to-pin tPD of 15 ns; design I/O timing budgets with 20% margin to account for temperature and supply variation across the commercial temperature range. The JTAG ISP interface allows board-level reprogramming without removing the device, but a clean 5.0 V rail and proper decoupling (0.1 uF plus 10 uF bulk per supply pin) are required during in-system programming operations. This page synthesizes distributor pricing, drop-in alternative MAX 9000 family variants, JTAG programming guidance, and practical design notes not found in the bare manufacturer datasheet, helping engineers source and integrate legacy 5 V CPLDs more efficiently.

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EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F

EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel

The Intel (formerly Altera) EPM9560RC304-15F is a 560-macrocell, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, housed in a 304-pin fine-pitch RQFP (plastic QFP) package. It delivers 12,000 usable gates, a propagation delay of 16.6 ns (tpd), and a maximum internal clock frequency of 117.6 MHz on a 5.0 V core supply, with 5.0 V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor device that combines multiple PLD macrocell blocks with a programmable interconnect matrix. Within the broader semiconductor taxonomy, a CPLD sits below an FPGA in density but above a simple SPLD or PAL; it is engineered for deterministic timing, low power consumption, and instant (zero-power-up) configuration from on-chip EEPROM, making it a member of the programmable logic IC family used to implement glue logic, bus interfacing, state machines, and peripheral bridging. Key features of the EPM9560RC304-15F include 212 user I/O pins, four dedicated inputs, a JTAG-compliant Boundary Scan Test (BST) port supporting ISP, open-drain or totem-pole outputs, and a programmable macrocell architecture built on Altera's third-generation Multiple Array MatriX (MAX) routing fabric. The device supports 5.0 V in-system programming, allowing designers to erase, program, and re-program the part on a populated PCB without removing the chip. Technically, the EPM9560RC304-15F implements logic through 16 Logic Array Blocks (LABs) of 40 macrocells each, sharing 16 product-term-wide Programmable Interconnect Array (PIA) routes. This PIA-based architecture provides predictable pin-to-pin delays independent of routing complexity, which is critical for replacing discrete 74-series TTL or CMOS glue logic with deterministic timing. The EEPROM process gives the part 100+ erase/program cycles and 20-year data retention. Typical applications include industrial control glue logic, bus-interface bridging (PCI, ISA, VME), power-sequencer controllers, telecommunications backplane glue, and military/aerospace systems requiring non-volatile instant-on logic. The wide I/O count (212) supports parallel buses and high-pin-count peripheral replacements. When designing with this part, allocate JTAG pins (TCK, TMS, TDI, TDO, TRST) for ISP access and ensure 5.0 V tolerant power-rail sequencing. The RQFP-304 footprint is large (40 x 40 mm class) - plan PCB real-estate accordingly and use a socket for prototyping when budget allows.

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EPM9560RC304-15N - MAX 9000 CPLD 560 Macrocells | Altera/Intel
EPM9560RC304-15N

EPM9560RC304-15N - MAX 9000 CPLD 560 Macrocells | Altera/Intel

The Altera (now Intel) EPM9560RC304-15N is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 12,000 usable gates and 560 macrocells in a 304-pin RQFP (Ruggedized Quad Flat Pack) package. It supports a maximum operating frequency of 117.6 MHz at 5 V supply and is built on the third-generation Multiple Array MatriX (MAX) architecture with in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/PLDs (small PAL/GAL-style glue logic) and FPGAs in the programmable logic taxonomy. Compared with FPGAs, CPLDs are typically flash- or EEPROM-backed, deterministic, have predictable pin-to-pin propagation delays in the nanosecond range, and boot instantly at power-up - making them ideal for bus decoding, address mapping, power-sequencing logic, and high-speed control rather than large parallel DSP or register-heavy data-pipeline designs. Key features of the EPM9560RC304-15N include 560 macrocells across 16 logic array blocks (LABs), 12,000 usable gates, 304 user I/O pins via the RQFP-304 package, and -15 speed grade indicating a 15 ns pin-to-pin propagation delay. The MAX 9000 family also provides programmable interconnect, 5 V tolerant inputs and outputs, and the JTAG-based ISP for boundary-scan and field reprogramming. The -15N suffix indicates the commercial operating temperature grade and lead-free / RoHS-compliant package marking. Typical applications include high-speed address decoding for memory and peripheral buses, 32-bit and 64-bit microprocessor glue logic, bus-interface bridging (PCI, ISA, VME, EISA), industrial control state machines, and ASIC-prototype replacement. The 304-pin RQFP package and 117.6 MHz fMAX make this CPLD well suited to designs requiring many parallel I/O channels in a single non-volatile device. When designing with this part, observe 5 V supply rail decoupling (>=0.1 uF ceramic per VCC pin), keep JTAG TCK below 10 MHz for reliable ISP, and ensure unused I/O pins are configured as outputs or terminated per Altera application note guidelines to avoid floating-input noise. The 304-pin RQFP footprint is shared with the broader MAX 9000 family, simplifying PCB reuse across EPM9400/EPM9480/EPM9560 density points and speed grades. This page consolidates verified distributor pricing, JTAG-programmable drop-in alternatives within the MAX 9000 family, and practical design notes not duplicated from the original datasheet. Engineers familiar with legacy Altera design flows (MAX+PLUS II or Quartus MAX device support) will find the EPM9560RC304-15N fully supported by legacy toolchains, though new designs targeting Intel MAX II/MAX V CPLDs benefit from lower static power and modern packaging.

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EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2

EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera

The Intel / Altera EPM9560RC304-2 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering approximately 12,000 usable gates in a 304-pin RQFP package. Operating at 5.0 V core with 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, the device is built on Altera's third-generation Multiple Array MatriX (MAX) architecture. The -2 speed grade positions this part for cost-sensitive designs where the slowest of the MAX 9000 grades is acceptable. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with multiple Logic Array Blocks (LABs) and a programmable interconnect matrix (PIA). In the system hierarchy, CPLD sits alongside FPGA in the programmable logic family but differs by offering non-volatile configuration, deterministic timing, instant-on behavior, and typically higher I/O count per logic block - making CPLD ideal for glue logic, bus decoding, address decoding, and state-machine control functions. Key features of the EPM9560RC304-2 include 304 user I/O pins, 16 Logic Array Blocks, multi-vendor IEEE 1149.1 JTAG boundary-scan support, and 5 V tolerant I/O with PCI-compatible drive. The device is pin-compatible with other speed grades (the -10, -15, -20) in the same 304-pin RQFP package, allowing drop-in performance upgrades without PCB rework. The RC suffix designates the 304-pin RQFP (Reinforced Quad Flat Pack) industrial package. The MAX 9000 architecture combines a global PIA with LABs each containing 16 macrocells. Each macrocell provides configurable registers with programmable clock, clear, and preset signals. Through the JTAG interface, designers can perform in-system programming (ISP) and boundary-scan test, eliminating the need for a separate programmer socket. The device retains its configuration in on-chip EEPROM, supporting unlimited reconfigurations. Typical applications include bus interface bridging, address decoding for microprocessor/microcontroller systems, peripheral glue logic, state-machine controllers, and legacy 5 V system design. The wide I/O count also makes it suitable for industrial control front-end aggregation and legacy telecom backplane glue. The -2 speed grade offers the slowest propagation delay in the family and is typically chosen for power-optimized or non-timing-critical glue logic roles. When designing with the EPM9560RC304-2, ensure the 5.0 V supply is well decoupled with 0.1 uF and 10 uF capacitors close to the VCC pins. Boundary-scan chain length must be calculated for the JTAG path, and unused I/O should be configured as outputs driving low or left floating per the JTAG chain configuration. Pin-compatible -10, -15, and -20 speed grades allow direct in-system speed upgrade without PCB rework.

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EPM9560RC304-20 - MAX 9000 CPLD 560 Macrocell 304-Pin RQFP | Altera
EPM9560RC304-20

EPM9560RC304-20 - MAX 9000 CPLD 560 Macrocell 304-Pin RQFP | Altera

The Altera EPM9560RC304-20 is a MAX 9000 family EEPROM-based complex programmable logic device (CPLD) offering 560 macrocells, 12,000 usable gates, and 212 user I/O lines in a 304-pin RQFP package, with a 20 ns pin-to-pin propagation delay and 100 MHz maximum operating frequency at 5.0 V. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom digital logic without fabricating an ASIC. Within the logic IC hierarchy, the MAX 9000 CPLD sits between simple PLDs and FPGAs: it offers non-volatile EEPROM configuration, deterministic timing, and instant-on operation, making it a programmable logic device (PLD) suited to glue logic, bus interfacing, and state-machine consolidation. Key features of the EPM9560RC304-20 include 560 macrocells organized in 20 logic array blocks (LABs), 12,000 usable gates, 212 I/O pins, and 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. The device supports configurable I/O operation at 3.3 V or 5 V, enabling mixed-voltage system integration. Its EEPROM configuration retains logic after power-down, eliminating external configuration memory. The MAX 9000 architecture uses a third-generation Multiple Array MatriX (MAX) structure with fast, predictable interconnect delays. The -20 speed grade delivers 20 ns pin-to-pin tPD and 100 MHz operation, while the 304-pin RQFP package provides 212 I/O for wide bus applications. EEPROM-based logic allows unlimited reprogramming cycles during development. Typical applications include PCI and ISA bus bridging, telecommunications line-card glue logic, industrial control state machines, and legacy system replacement where instant-on 5 V CPLD logic is required. The 212 I/O count suits wide address/data bus interfacing. When designing with the EPM9560RC304-20, note that it is a 5.0 V core device with 3.3 V/5 V configurable I/O; verify I/O bank voltage compatibility with connected devices. Because the part is a legacy MAX 9000 device, confirm lifecycle availability before committing to new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers a single reference for the EPM9560RC304-20 CPLD.

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EPM9560RC304-20C - MAX 9000 CPLD, 560 Macrocells, 5V | Intel / Altera
EPM9560RC304-20C

EPM9560RC304-20C - MAX 9000 CPLD, 560 Macrocells, 5V | Intel / Altera

The Intel / Altera EPM9560RC304-20C is a high-performance CMOS EEPROM-based programmable logic device (PLD) from the MAX 9000 family, featuring 12K usable gates, 560 macrocells, and 212 user I/O pins in a 304-pin RQFP package with 100 MHz internal operation at 5 V core voltage. The part integrates third-generation Multiple Array MatriX (MAX) architecture with 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, enabling direct PCB-level configuration without external programmers. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays with a central interconnect matrix. CPLDs are members of the broader PLD hierarchy (PLD -> CPLD -> programmable logic -> digital semiconductor) and serve as glue logic, bus decoder, state-machine and high-speed control engines between processors, memories and peripherals. Unlike SRAM-based FPGAs, MAX 9000 CPLDs retain configuration in on-chip EEPROM, providing instant-on behaviour with zero external boot memory. Key features include 560 macrocells distributed across 16 Logic Array Blocks (LABs), 212 user I/O pins supporting 3.3 V or 5 V mixed-mode operation, 100 MHz fMAX for counter and registered performance, and tPD of 20 ns (commercial speed grade -20C). The on-chip EEPROM cell array provides 100 erase/program cycles endurance and supports JTAG-based in-system programming (ISP) compliant with IEEE 1149.1 boundary-scan. The -20C suffix indicates the 20 ns pin-to-pin delay in the commercial 0 C to +70 C temperature range. Architecture-wise, the MAX 9000 family uses Altera's third-generation Multiple Array MatriX interconnect - a continuous, fast, uniform routing matrix that links every LAB to every I/O pin and every other LAB. This produces predictable, software-independent timing that simplifies static timing closure, an important advantage over segmented FPGA routing. Each macrocell contains a programmable AND/OR array plus a configurable flip-flop, supporting combinational, registered, latched and tri-state I/O patterns from the same primitive. Typical applications include industrial bus-bridging and protocol conversion (PCI, VME, ISA, VXI glue logic), high-speed address decoding, state-machine control in motor drives, and telecom backplane glue logic. With 212 I/O pins and 5 V tolerance, the EPM9560RC304-20C is especially useful in legacy 5 V system backplanes where modern low-voltage CPLDs cannot be used. The 304-pin RQFP footprint suits industrial-grade PCBs with sufficient board area. When designing with this device, place four 0.2 uF decoupling capacitors near each VCC/ GND pair, observe the 304-pin RQFP thermal pad layout, and ensure JTAG chain integrity (TCK pull-down, TMS/TDI pull-up per IEEE 1149.1). Programming voltage VPP is generated on-chip; no external 12 V supply is required, simplifying manufacturing flow. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the original MAX 9000 datasheet, giving procurement and hardware engineers a single source for sourcing and replacement decisions.

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EPM9560RC304-20N - MAX 9000 CPLD 560 Macro Cells | Altera
EPM9560RC304-20N

EPM9560RC304-20N - MAX 9000 CPLD 560 Macro Cells | Altera

The Altera EPM9560RC304-20N is a 5.0 V EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, offering 12,000 usable gates, 560 macrocells, and 212 user I/O pins in a 304-pin RQFP (PowerQuad) package. It delivers a 20 ns pin-to-pin propagation delay and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. Within the semiconductor taxonomy, a CPLD sits between simple PLDs (SPLDs) and FPGAs: it offers non-volatile configuration, deterministic timing, and instant-on operation, making it the preferred choice for glue logic, bus bridging, and state-machine control. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses a continuous metal interconnect to deliver predictable, uniform delays across the entire device. Key features of the EPM9560RC304-20N include 560 macrocells organized into 20 logic array blocks (LABs), 12,000 usable gates, and 212 I/O pins that can be individually configured for 3.3 V or 5.0 V operation. The device is programmed via an EEPROM configuration element, so it retains its design after power-down without an external configuration PROM. The 20 ns speed grade (-20) supports system clock frequencies up to 100 MHz, and the JTAG boundary-scan port enables both in-system programming and board-level interconnect testing. The MAX 9000 architecture uses a fixed, non-segmented interconnect matrix that guarantees worst-case pin-to-pin delays without the routing-dependent timing variability found in SRAM-based FPGAs. This deterministic timing behavior simplifies static timing analysis and eliminates the need for post-fit timing closure iterations, which is a significant advantage for safety-critical and long-lifecycle industrial designs. Typical applications include industrial control backplanes, telecommunications line cards, PCI/ISA bus bridging, test-and-measurement instrumentation, and legacy system replacement where a 5.0 V, non-volatile programmable logic device is required. The 304-pin RQFP package provides 212 I/O pins, enough to interface wide parallel buses without external multiplexing. When designing with the EPM9560RC304-20N, note that the device requires a stable 5.0 V core supply and that the JTAG ISP interface must be accessible for field upgrades. Because the part is a mature, legacy MAX 9000 device, designers should verify current availability and consider pin-compatible MAX 9000 speed-grade variants for new designs. This page synthesizes distributor availability, drop-in speed-grade alternatives, and practical design notes that are not consolidated in the manufacturer datasheet, giving engineers a single reference for sourcing and migration decisions.

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EPM9560RC304-2N - MAX 9000 CPLD, 304-pin, 5.0V | Intel / Altera
EPM9560RC304-2N

EPM9560RC304-2N - MAX 9000 CPLD, 304-pin, 5.0V | Intel / Altera

The Intel (formerly Altera) EPM9560RC304-2N is a high-density Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in a 304-pin RQFP/RBGA-class plastic carrier with 560 macrocells and 12,000 usable gates. It is built on a 5.0V CMOS EEPROM process and is rated for industrial-temperature operation, with the speed grade "-2" placing it in the mid-band of the family's tPD options. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/PLA-style logic blocks with a central interconnect matrix. CPLDs are used for glue logic, bus interfacing, state-machine control, and address decoding - typically chosen over discrete TTL/CMOS when the design must be reconfigured, kept compact, or shipped across product variants. Within the programmable-logic hierarchy, CPLDs sit below FPGAs in density but offer deterministic timing, instant-on from non-volatile memory, and high I/O counts per dollar. Key features of the EPM9560RC304-2N include a maximum pin-to-pin propagation delay (tPD) on the order of -2 speed-grade performance, in-system programmability via the IEEE 1149.1 JTAG interface, and a wide operating voltage range centred at 5.0V. The device supports multiple I/O standards and provides programmable pull-ups, slew-rate control, and per-pin output enable. Architecturally, the MAX 9000 family partitions the 560 macrocells across Logic Array Blocks (LABs) wired by a FastTrack interconnect, delivering predictable timing and uniform routing delay regardless of placement. The 304-pin package provides the largest pin-count option in the family, maximising user I/O for high-density bus-interface or bus-multiplexing applications. Typical applications include telecommunications backplane glue logic, industrial-control address decoding, peripheral interface bridging (PCI-to-ISA, memory-to-bus arbitration), and high-pin-count state-machine controllers in embedded systems. The instant-on non-volatile configuration suits safety-critical and power-sequenced systems. Designers should note that the 304-pin package is the largest pin-count in the MAX 9000 family; PCB layout requires careful power/ground planning and thermal relief. The 5.0V core is incompatible with 3.3V-only systems unless level-shifters are used on every I/O. This page consolidates drop-in alternatives, parameter comparison, and design considerations not found in the manufacturer datasheet, helping engineers source and qualify the EPM9560RC304-2N efficiently.

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EPM9560RC304-3 - MAX 9000 EPLD, 560 Macro Cells, 304-pin RQFP | Intel
EPM9560RC304-3

EPM9560RC304-3 - MAX 9000 EPLD, 560 Macro Cells, 304-pin RQFP | Intel

The Intel EPM9560RC304-3 is a MAX 9000 family EPLD (Erasable Programmable Logic Device) with 12,000 usable gates and 560 macro cells in a 304-pin RQFP package, factory speed grade -3. It is a member of the classic Altera MAX 9000 high-density programmable logic family, designed for 5 V system designs that require deterministic logic integration beyond the capacity of smaller CPLDs. An EPLD (Erasable Programmable Logic Device) is a non-volatile, in-system programmable logic device that combines the density of early gate arrays with the instant-on, deterministic timing of classic PAL/GAL architectures. The MAX 9000 family belongs to the broader hierarchy: EPLD -> CPLD (Complex Programmable Logic Device) -> programmable logic -> digital semiconductor. Its 5 V core allows direct interface to TTL and CMOS logic families without level shifters, simplifying legacy industrial and telecom designs. Key features include 12,000 usable gates, 560 macro cells, a maximum internal operating frequency in the 95 MHz class for the -3 speed grade, and an in-system programmability (ISP) interface via the JTAG-compliant 4-wire port. The device is built on UV-erasable CMOS EPROM technology, allowing multiple design iterations during development. Pin-to-pin compatible speed grades (-3, -7, -10, -12, -15, -20) let designers migrate between timing budgets without PCB changes. The MAX 9000 architecture uses a Logic Array Block (LAB) and Programmable Interconnect Array (PIA) structure. Each macro cell contains a programmable AND/OR array plus a configurable flip-flop, enabling both combinatorial and registered logic with predictable, deterministic pin-to-pin delays. The PIA routes signals between LABs with uniform delay, eliminating the placement-dependent timing issues common to FPGAs of the same era. Typical applications include 5 V telecom bus controllers, industrial PLC glue logic, peripheral adapters for legacy microprocessors, and bus-interface state machines. The 304-pin RQFP package provides abundant user I/O for wide bus or multi-channel designs. The MAX 9000 device is a strong fit for designs where 5 V tolerance, deterministic timing, and high macro-cell density outweigh the need for modern FPGA features such as transceivers or large block RAM. When designing with the EPM9560RC304-3, observe the device's 5 V VCCINT requirement and decoupling recommendations; a 0.1 uF ceramic capacitor adjacent to each supply pin plus a bulk 10 uF tantalum near the package is the standard pattern from MAX 9000 reference designs. For new designs requiring 3.3 V operation or higher density, consider migrating to the MAX V or MAX 10 family. This page synthesizes distributor pricing for the EPM9560RC304-3, drop-in same-package speed-grade alternatives, and practical design notes that go beyond the original MAX 9000 datasheet.

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EPM9560RC304-5 - MAX 9000 CPLD 12K Gates 304-Pin RQFP | Altera
EPM9560RC304-5

EPM9560RC304-5 - MAX 9000 CPLD 12K Gates 304-Pin RQFP | Altera

The Altera EPM9560RC304-5 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates and 560 macrocells in a 304-pin RQFP (PowerQuad II) package, with a -5 speed grade rated for 5 V operation. It is a 5.0 V in-system-programmable EPLD built on Altera's MAX 9000 architecture, combining EEPROM-based non-volatile configuration with predictable pin-to-pin delays. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that contains an array of macrocells and a programmable interconnect matrix, allowing designers to implement custom combinational and sequential logic without fabricating a custom ASIC. In the product hierarchy, the EPM9560 sits within the MAX 9000 EPLD family, which is part of the broader programmable logic device (PLD) category, alongside FPGAs and simple PLDs (SPLDs). MAX 9000 devices use EEPROM configuration cells, so they retain their design after power-down and require no external configuration memory. Key features of the EPM9560RC304-5 include 560 macrocells, 12,000 usable gates, 5.0 V supply operation, and a maximum operating frequency of 117.6 MHz for the -15 grade family member (the -5 grade is the fastest speed grade in the family). The device provides 304 pins in the RQFP package, offering a high I/O count for bus-intensive glue logic, and supports in-system programming (ISP) via the JTAG interface for field upgrades. The MAX 9000 architecture uses a logic array block (LAB) structure with macrocells feeding a fast, deterministic interconnect, giving fixed, predictable propagation delays independent of routing - a key advantage over SRAM-based FPGAs for timing-critical glue logic. The EEPROM process also provides excellent retention and immunity to single-event upsets compared with volatile configuration technologies. Typical applications include PCI and VME bus bridging, memory controller glue logic, address decoding, state machines, and legacy system replacement where a 5 V CPLD with high I/O count is required. The 304-pin RQFP package suits dense backplane and bus-interface boards. When designing with this device, note that it is a 5 V part and is not 3.3 V tolerant on all pins without level shifting; verify the I/O standard requirements of the surrounding logic. Also confirm the exact speed grade suffix (-5, -10, -15) against the timing budget, since propagation delay scales with grade. This page synthesizes distributor availability, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC304-5, providing information gain beyond the manufacturer datasheet alone.

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EPM9560RC304C-3 - MAX 9000 CPLD, 560 Macrocells, 304-Pin RBGGA | Altera
EPM9560RC304C-3

EPM9560RC304C-3 - MAX 9000 CPLD, 560 Macrocells, 304-Pin RBGGA | Altera

The Altera (Intel) EPM9560RC304C-3 is a high-density MAX 9000 family Complex Programmable Logic Device (CPLD) housed in a 304-pin RBGGA (Rugged Ball Grid Array) package with 560 logic elements (macrocells), 12,000 usable gates, and an in-system programmable, non-volatile EEPROM-based architecture. The device supports a pin-to-pin propagation delay of 3 ns (commercial speed grade) and operates from a single 5 V supply, with I/O standards including TTL and CMOS-compatible interfaces across 212 user I/O pins. Key features of the MAX 9000 family include the classic MAX (Multiple Array Matrix) interconnect structure with Logic Array Blocks (LABs) and a global Programmable Interconnect Array (PIA), in-system programmability via IEEE 1149.1 JTAG, and a built-in boundary-scan test capability that simplifies board-level test. The "C" suffix indicates commercial temperature grade (0 C to +70 C), the "RC" indicates a ceramic BGA package, and "-3" indicates the speed grade. The EPM9560 is the highest-density member of the MAX 9000 family and is widely deployed in legacy telecom, industrial control, and glue-logic applications where a non-volatile, deterministic CPLD is required. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with much higher gate density, providing deterministic timing and instant-on behavior from a single flash/EEPROM configuration cell. CPLDs sit alongside FPGAs in the programmable logic hierarchy, but are distinguished by their non-volatility, faster pin-to-pin deterministic timing, and lower power consumption at small logic capacities - making them ideal for control-plane logic, bus interfacing, address decoding, and state-machine replacement rather than high-density parallel DSP. Typical applications for the EPM9560RC304C-3 include legacy telecom backplane glue logic, industrial control and factory automation, address decoding for microprocessor and DSP systems, bus-interface bridging (e.g., PCI to local bus), and replacement of multiple discrete TTL/CMOS glue-logic ICs. The MAX 9000 family was one of the most widely deployed CPLD families of the late 1990s and early 2000s and is still in use today in long-lifecycle industrial and military systems. When designing with the EPM9560RC304C-3, designers should note that the device is part of an older MAX 9000 generation - Altera/Intel MAX II, MAX V, and MAX 10 families offer newer non-volatile CPLD alternatives with lower power and lower cost. However, for true pin-compatible drop-in replacements on existing 304-pin BGA layouts, the EPM9560RC304-15, EPM9560RC304-10, and EPM9560RC304-20 speed-grade variants are functionally identical. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on a single manufacturer page.

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EPM9560RC340-15 - MAX 9000 CPLD, 560 Macrocells, 15ns | Altera
EPM9560RC340-15

EPM9560RC340-15 - MAX 9000 CPLD, 560 Macrocells, 15ns | Altera

The Altera EPM9560RC340-15 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 560 macrocells and approximately 12,000 usable gates with a 15 ns pin-to-pin delay in a 340-pin RQFP package. It is built on a third-generation Multiple Array MatriX (MAX) architecture and supports 5.0V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A Complex Programmable Logic Device (CPLD) is a non-volatile, EEPROM- or flash-based integrated circuit that combines multiple PAL/GAL-style logic blocks with a programmable interconnect matrix, providing deterministic timing, instant-on operation, and high fan-in per output. CPLDs sit below FPGAs in the programmable logic hierarchy: FPGAs offer higher logic density and SRAM-based reconfigurability, whereas CPLDs excel at glue logic, bus decoding, state machines, and power-sequencing applications where fast, predictable propagation delay and zero-configuration boot time matter more than raw gate count. Key features of the EPM9560RC340-15 include a 15 ns maximum pin-to-pin propagation delay (tPD), 5.0V VCC operation (4.75V to 5.25V tolerance), up to 212 user I/O pins, JTAG-based boundary-scan test per IEEE 1149.1, and 12,000 gates of MAX architecture logic. The 340-pin RQFP (Reduced Quad Flat Pack) package provides surface-mount integration with thermal performance suitable for industrial operating conditions (0C to +70C commercial range). Internally, the device is organized as multiple Logic Array Blocks (LABs) interconnected by a programmable switch matrix, with each macrocell containing programmable AND/OR arrays plus a configurable flip-flop. The EEPROM process technology ensures reprogrammability without external memory, while the JTAG port enables in-system reconfiguration, production-line programming, and board-level boundary-scan testing per IEEE 1149.1. Typical applications include high-density glue logic for microprocessor/microcontroller systems, bus-interface bridging (e.g., 8-bit to 16-bit or 16-bit to 32-bit translation), state-machine controllers, and replacement of multiple discrete PAL/GAL devices in industrial control and telecommunications equipment. With 212 user I/Os and 560 macrocells, the EPM9560 is well suited to consolidating dozens of small logic functions onto a single programmable device, simplifying PCB layout and reducing BOM count. When designing with this device, allocate sufficient I/O headroom and verify JTAG chain topology against the IEEE 1149.1 specification before layout finalization. The MAX 9000 family uses Altera legacy MAX+PLUS II development tooling, which is now distributed by Intel FPGA; designers should confirm tool availability for new projects. This page synthesizes distributor availability, same-package drop-in alternatives from the Site MPN list, and practical design notes for the MAX 9000 architecture not found in the standalone datasheet.

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EPM9560RCRC304-15 - MAX 9000 CPLD 560 Macro Cells | Altera
EPM9560RCRC304-15

EPM9560RCRC304-15 - MAX 9000 CPLD 560 Macro Cells | Altera

The Altera EPM9560RCRC304-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates and 560 macro cells with a 15 ns pin-to-pin propagation delay, housed in a 304-pin RQFP (PowerQuad) package. It is a 5.0 V EEPROM-based programmable logic device built on Altera's third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL. In the product hierarchy, a CPLD sits between simple PLDs and FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. MAX 9000 devices use EEPROM configuration cells, so they retain their design without an external configuration memory and are live at power-up, unlike SRAM-based FPGAs. Key features of the EPM9560RCRC304-15 include 560 macro cells, 12,000 usable gates, a 15 ns pin-to-pin logic delay, and 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. The device supports up to 216 user I/O pins and operates from a single 5 V supply, making it directly compatible with legacy 5 V TTL and CMOS logic levels. The MAX 9000 architecture uses a hierarchical Multiple Array MatriX of logic array blocks (LABs) interconnected by a fast, predictable routing structure. This deterministic interconnect gives fixed, data-sheet-guaranteed timing independent of placement and routing, which is a major advantage over SRAM FPGAs for glue-logic, state-machine, and bus-interface designs where timing closure must be repeatable. Typical applications include legacy industrial control backplanes, 5 V bus bridging and address decoding, telecommunications line-card glue logic, test and measurement instrumentation, and replacement of discrete 74-series logic in existing designs. The 304-pin RQFP package provides high I/O density for wide bus interfaces. When designing with this device, note that it is a mature, non-volatile 5 V part: verify availability of the MAX+PLUS II development toolchain and confirm the JTAG ISP chain before committing a new design. Because the part is EOL/obsolete at the manufacturer, second-source or drop-in alternatives should be qualified early. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and migrating the EPM9560RCRC304-15.

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EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera
EPM9560RI205-15

EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera

The Altera EPM9560RI205-15 is a member of the MAX 9000 family of high-performance CMOS EEPROM-based Complex Programmable Logic Devices (CPLDs) implementing up to 6,000 usable gates, housed in a 205-pin RQFP package with a 15 ns pin-to-pin propagation delay. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, the device integrates multiple Logic Array Blocks (LABs) and a programmable interconnect network to deliver deterministic, high-speed combinational and registered logic for glue-logic and bus-interface applications. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on semiconductor that combines the integration density of an FPGA with the deterministic timing and low power of a traditional SPLD. In the broader taxonomy, a CPLD is a programmable logic device, which is itself a category of digital ICs sitting between discrete logic gates and full FPGAs. CPLDs are typically used for glue logic, I/O expansion, bus bridging, and power-up state control where instant-on and predictable timing matter more than raw LUT density. Key features of the EPM9560RI205-15 include 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 212 macrocells distributed across LABs, and dedicated I/O pins with programmable drive strength and slew-rate control. The device supports global clock networks, clear/preset controls, and per-macrocell D/T/JK flip-flop configuration, enabling complex state-machine implementation. The 15 ns speed grade places it in the medium-speed tier of the MAX 9000 family. Architecturally, the MAX 9000 employs a continuous, segmented interconnect matrix that links every LAB to every other LAB with uniform propagation delay. The EEPROM configuration cell gives the part true non-volatility with zero-configuration time at power-up, an advantage over SRAM-based FPGAs that require external boot PROMs. Per-pin JTAG boundary-scan and a built-in IEEE 1149.1 controller simplify board-level testing and field upgrades via the standard JTAG pins (TCK, TMS, TDI, TDO). Typical applications include bus interface bridges (e.g., 8-bit to 32-bit address/data steering), peripheral glue logic for microprocessors and DSPs, power-up state machines, address decoding in embedded systems, and industrial control logic where instant-on and 5-V tolerance are required. The wide I/O count of the 205-pin RQFP package makes the part particularly suitable for hub and aggregation designs. When designing with the EPM9560RI205-15, observe the 5.0-V VCCIO tolerance and provide adequate decoupling - at least 0.1 uF ceramic on every VCC/ground pair within 100 mils of the package pin. Use the JTAG chain to retain ISP capability even after PCB assembly. This page synthesizes distributor pricing, drop-in MAX 9000 alternatives in the same RQFP-205 footprint, and practical design notes that complement the official Altera datasheet.

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EPM9560RI208-10 - 12K-Gate MAX 9000 CPLD, 10ns, 208-Pin RQFP
EPM9560RI208-10

EPM9560RI208-10 - 12K-Gate MAX 9000 CPLD, 10ns, 208-Pin RQFP

The Intel (formerly Altera) EPM9560RI208-10 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on an advanced 0.5 µm CMOS technology. It provides approximately 12,000 usable gates, 560 macrocells, and pin-to-pin delays as fast as 10 ns with counter frequencies up to 144 MHz, all housed in a 208-pin Power Quad Flat Pack (RQFP) surface-mount package rated for the industrial temperature range (-40 °C to +85 °C). A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that combines multiple PAL-like macrocell blocks connected through a central programmable interconnect array (PIA). CPLDs sit between small SPLDs/GALs and large SRAM-based FPGAs in the programmable logic hierarchy: they offer deterministic 10 ns-class pin-to-pin timing, ISP via JTAG, and zero-configuration boot time, making them ideal for glue logic, bus decoding, and control-plane state machines. The MAX 9000 family extends the MAX 7000 architecture to higher densities by tiling more Logic Array Blocks (LABs) onto a unified PIA fabric. Key features of the EPM9560RI208-10 include the 10 ns tPD speed grade, 560 macrocells distributed across LABs, 212 user I/O pins (typical for the 208-RQFP package), in-system programmability via the IEEE 1149.1 (JTAG) interface, 5.0 V VCCINT operation, and a programmable power-saving mode that reduces Icc by up to 50 % on unused macrocells. The 208-pin RQFP package provides generous board-routing room for legacy 5 V designs that have long since moved off SOIC/QFN footprints. Architecturally, the device integrates a global PIA, multiple LABs each containing 16 macrocells, I/O control blocks, and four dedicated input pins that feed the global clock/clear network. The EEPROM configuration cell supports 100 erase/program cycles and is retained for at least 10 years per the legacy MAX 9000 datasheet. Boundary-scan JTAG, an open-drain ISP interface, and PCI-compliant I/O make the part a common choice for 5 V bus-interface bridges. Typical applications include 5 V PCI bus interface glue logic, address decoding and wait-state generation in 68k/8051/x86 embedded systems, industrial motor-control state machines, and legacy telecommunications backplane controllers. Engineers often place the EPM9560RI208-10 between an asynchronous SRAM bank and a microcontroller to implement programmable timing, glue logic, or bus-width adapters. When designing with this device, observe the legacy 5 V I/O tolerance: it cannot be directly interfaced to 3.3 V logic without external level shifters or bus switches, and the 208-pin RQFP requires a generous PCB land pattern. Verify timing with the Quartus II legacy support package, since newer Quartus releases target modern Cyclone/MAX V families. This page consolidates distributor pricing and parametric data not always presented on a single manufacturer page.

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EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP
EPM9560RI208-10N

EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP

The Altera (now Intel) EPM9560RI208-10N is a member of the MAX 9000 family of high-performance, in-system programmable CMOS EPLDs based on the third-generation Multiple Array MatriX (MAX) architecture. It integrates 12,000 usable gates, 560 macro cells, and a 16-macro-cell Logic Array Block (LAB) structure with 12,160 register bits, and it operates at a pin-to-pin propagation delay of approximately 10 ns. The device is housed in a 208-pin RQFP (Plastic Quad Flat Pack) package with 212 user I/Os and operates from a single 5V supply with in-system programmability via IEEE 1149.1 (JTAG) boundary scan. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the low cost and ease of use of PAL/GAL structures with the high integration and routing flexibility of FPGA-like fabric. Within the broader programmable logic taxonomy, the CPLD sits between simple PLDs (PAL, GAL) and high-density FPGAs, providing fast, deterministic pin-to-pin timing (predictable interconnect delays) with non-volatile EEPROM configuration memory. The MAX 9000 family, in particular, introduced the LAB-based interconnect scheme that became Altera's architectural hallmark for high-pin-count glue-logic designs. The key features that distinguish EPM9560RI208-10N include 560 macro cells, a maximum operating frequency of approximately 100-125 MHz (per the MAX 9000 family rating), 212 user I/Os, and a 5V core supply. The "RI" package suffix denotes the Industrial operating-temperature grade (-40C to +85C), and the "-10" speed grade specifies the 10 ns pin-to-pin delay. The "N" suffix indicates a lead-free, RoHS-compliant assembly. JTAG-based in-system programming enables field upgrades without removing the device from the board, and the on-chip EEPROM cells retain the configuration indefinitely without a separate boot PROM. Typical applications for the EPM9560RI208-10N include 32-bit PCI bus interface glue logic, high-speed address decoding in embedded processor systems, bus isolation and multiplexing (e.g., between a DSP and a memory bus), state-machine controllers for industrial automation, and glue logic between disparate logic families in mixed-voltage designs. Designers choose the MAX 9000 family specifically when deterministic timing, non-volatility, and high pin count are required without the complexity of an FPGA. With 12K gates and 212 I/Os, the EPM9560 handles wide bus interfaces and parallel control tasks more elegantly than multiple discrete PLDs. When designing with this device, allow adequate ground and VCC pins on both sides of the package to ensure low-impedance power delivery for the simultaneous-switching output currents typical of 208-pin bus glue designs. Use the JTAG chain to program the device in-system, but observe the manufacturer's recommended 5V supply ramp and decoupling network (typically 0.1 uF ceramic plus 10 uF bulk per VCC pin group) to keep the EEPROM programming voltage well-regulated. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

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EPM9560RI208-15 - 560-Macrocell MAX 9000 CPLD, 208-Pin RQFP | Intel
EPM9560RI208-15

EPM9560RI208-15 - 560-Macrocell MAX 9000 CPLD, 208-Pin RQFP | Intel

The Intel (formerly Altera) EPM9560RI208-15 is a high-performance, 560-macrocell CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in a 208-pin Power Quad Flat Pack (RQFP) with industrial temperature grading. It is built on the third-generation Multiple Array MatriX (MAX) architecture, supports 153 user I/O lines, and operates at a typical internal frequency of 145 MHz with a pin-to-pin propagation delay of 11.4 ns (commercial) to 15 ns (industrial -15 speed grade). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like logic blocks on a single die with a global interconnect matrix. In the system hierarchy, CPLDs sit between simple SPLDs (PAL/GAL) and FPGAs: they offer deterministic, tCO-class timing, instant-on configuration from on-chip EEPROM, and high-drive I/O suited to bus-interface and glue-logic roles. The MAX 9000 family extends the classic MAX architecture to densities between 5,000 and 12,000 usable gates, positioning the EPM9560 as the mid-to-high density member with 12,000 typical gates. Key features of the EPM9560RI208-15 include in-system programmability (ISP) via JTAG (IEEE 1149.1), 5.0 V VCCIO-tolerant multi-volt I/O (3.3 V or 5 V mixed-mode), 16 macrocell LABs of 16 macrocells each, four global clock pins, programmable power-saving per macrocell, and JTAG boundary-scan testability. The 208-pin RQFP gull-wing package gives a thermal resistance suitable for 0 to 70 °C commercial environments in the -15 speed grade. The architecture uses a high-performance CMOS EEPROM process, providing non-volatile configuration retention, fast in-system erase/program, and predictable combinational/sequential logic. The interconnect is a continuous, fast-path Programmable Interconnect Array (PIA) that routes any LAB output to any other LAB input without contention, simplifying timing closure for control and bus-interface designs. Typical applications include bus-interface glue logic (PCI bridges, address decoding), 5 V to 3.3 V level shifting, microcontroller peripheral expansion, state-machine controllers, JTAG-based boundary-scan boards, and industrial control glue where instant-on, non-volatile boot is required. With 153 user I/Os in a 208-pin footprint, the EPM9560 is well matched to wide-bus interface designs. When designing with this device, observe the 5 V nominal supply tolerance (typically 4.5 V to 5.5 V), provide adequate decoupling (0.1 µF per VCC pin plus bulk), and follow Altera MAX 9000 JTAG ISP guidelines for in-system programming. The MAX+PLUS II or Quartus II toolchain (legacy) is required for design entry, fitting, and verification. This page synthesizes distributor pricing, EPM9560 family cross-references, drop-in pin-compatible same-brand alternatives (EPM9560 family speed/package variants), and practical design notes not consolidated in any single manufacturer document.

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