EP1810LC-25 vs EP1810LC-45 비교
다음의 상세 나란히 비교: EP1810LC-25 제조: Altera 및 EP1810LC-45 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete사양 비교
| 파라미터 | EP1810LC-25 | EP1810LC-45 |
|---|---|---|
| 브랜드 | Altera | Rochester Electronics |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $8.40 | $49.90 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| 패키지 | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (J-lead) |
| Package Code | LC = 68-pin JLCC | — |
| 실장 유형 | Surface Mount | Surface Mount (PLCC socket compatible) |
| Technology | CMOS EPLD (erasable programmable logic device) | — |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| 수명 주기 상태 | Obsolete (legacy Altera Classic family) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| 동작 온도 | [DATA_NEEDED: temperature grade for LC package] | 0 °C to +70 °C (commercial) |
| Family | — | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |