EP1SGX10DF672C6N vs EP1SGX25DF67216 비교
다음의 상세 나란히 비교: EP1SGX10DF672C6N 제조: Altera 및 EP1SGX25DF67216 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1SGX10DF672C6N | EP1SGX25DF67216 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $195.00 | $198.00 |
| Manufacturer | Altera (Intel) | — |
| Series | Stratix GX | — |
| Family | Stratix GX | Stratix GX |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Cells | 10,570 | — |
| Configurable Logic Blocks (CLBs) | 1,200 | — |
| Total RAM Bits | 920,448 | 1,944,576 |
| Maximum User I/Os | 362 | — |
| Supply Voltage (Core) | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Logic Family | CMOS | — |
| Package Type | 672-FBGA (FineLine BGA, 27 × 27 mm, 1 mm pitch) | — |
| 핀 수 | 672 | — |
| 실장 유형 | Surface Mount | Surface Mount (BGA) |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| Transceivers | Up to 20 high-speed serial channels | — |
| RoHS 상태 | [DATA_NEEDED: rohs_status] | Lead-free / RoHS compliant (per Altera product family documentation) |
| Logic Elements | — | 25,660 |
| Embedded Multipliers (18x18) | — | [DATA_NEEDED: 18x18 multiplier count] |
| Number of PLLs | — | 4 |
| Number of Transceiver Channels | — | 8 (4 in each of 2 banks) |
| Max Transceiver Data Rate | — | 3.1875 Gbps per channel |
| Min Transceiver Data Rate | — | 500 Mbps |
| Core Supply Voltage | — | 1.5 V |
| Auxiliary Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for DF672 package] |
| 패키지 | — | 672-ball FineLine BGA (DF672) |
| 동작 온도 | — | Industrial, -40C to +100C (I-suffix family) |
| On-Die Termination | — | Yes, 100-ohm differential |
| Pre-emphasis / Equalization | — | Programmable (transmitter pre-emphasis; receiver adaptive equalization) |
| Configuration Schemes | — | Passive serial, fast passive parallel, JTAG, Altera enhanced configuration |