EP610DC-35 vs EP610DM-35 비교
다음의 상세 나란히 비교: EP610DC-35 제조: Altera 및 EP610DM-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610DC-35 | EP610DM-35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $18.40 | $23.40 |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| 패키지 | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (CERDIP) with UV window |
| 실장 유형 | Through-Hole (DIP) | — |
| 동작 온도 | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | — |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | Altera (Rochester Electronics authorized stock) |
| RoHS 상태 | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | Non-compliant (contains lead, hermetic CERDIP) |
| Part Family | — | Classic EPLD |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| I/O Pins | — | 24 dedicated I/O (input + bidirectional) |
| Programmability | — | UV-erasable, reprogrammable |
| 동작 온도 범위 | — | -55°C to +125°C |
| MSL 레벨 | — | [DATA_NEEDED: MSL rating] |