EP610JI-30 vs EP610PC-15 비교
다음의 상세 나란히 비교: EP610JI-30 제조: Altera 및 EP610PC-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610JI-30 | EP610PC-15 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.40 | $17.50 |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Product Terms | 160 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| 공급 전압 | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| 패키지 | CQCC28 (windowed ceramic JLCC, J-bend) | PDIP-24 (plastic DIP, 24-pin) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| 동작 온도 | -40C to +85C (industrial, per EP610 family suffix convention) | [DATA_NEEDED: operating temperature range] |
| 실장 유형 | Surface Mount (JLCC) | Through-Hole (DIP) |
| RoHS 상태 | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Usable Gates | — | 300 gates |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| 핀 수 | — | 24 pins |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |