EP610JI-30 vs EP610PC-15 Comparison

Detailed side-by-side comparison of EP610JI-30 by Altera and EP610PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610JI-30 EP610PC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.40 $17.50
Family Altera Classic EPLD (EP610) Classic EPLD
Device Type UV Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device)
Macrocells 16 16
Propagation Delay (tpd) 30 ns (max) β€”
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Product Terms 160 β€”
Dedicated Inputs 4 β€”
I/O Pins 16 β€”
External Clocks 2 β€”
Supply Voltage 5 V (single supply) β€”
Process Technology CMOS β€”
Package CQCC28 (windowed ceramic JLCC, J-bend) PDIP-24 (plastic DIP, 24-pin)
Package Code JLCC-28 / CQCC28 β€”
Erasure Method Ultraviolet (UV) via top window β€”
Programming Altera Logic Programmer compatible β€”
Operating Temperature -40C to +85C (industrial, per EP610 family suffix convention) [DATA_NEEDED: operating temperature range]
Mounting Type Surface Mount (JLCC) Through-Hole (DIP)
RoHS Status [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] β€”
Usable Gates β€” 300 gates
Logic Delay (tPD) β€” 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency β€” 100 MHz (per family datasheet)
Supply Voltage (VCC) β€” 5 V (single supply)
Technology β€” CMOS
Architecture β€” PAL-type, sum-of-products AND/OR array
TTL Emulation β€” 100% TTL compatible
Pin Count β€” 24 pins
Development Tool β€” Altera MAX+PLUS II
Logic Test Circuitry β€” On-board for AC/DC verification

Datasheets & Resources

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