EP610PC-35 vs EP610DC-35 비교
다음의 상세 나란히 비교: EP610PC-35 제조: Rochester Electronics 및 EP610DC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610PC-35 | EP610DC-35 |
|---|---|---|
| 브랜드 | Rochester Electronics | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.79 | $18.40 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD - Classic EPLD |
| Family | Classic EPLD | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 37 ns (max, -35 speed grade) | 35 ns |
| Internal Counter Frequency | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Supply Voltage - Internal | 4.75 V to 5.25 V | — |
| 동작 온도 | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Programmable Type | EPLD (UV-erasable window variant: EP610DC; plastic OTP) | — |
| 패키지 | 24-pin PDIP (Plastic DIP, 0.600" wide, through-hole) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 실장 유형 | Through Hole | Through-Hole (DIP) |
| Supplier Device Package | 24-PDIP | — |
| Logic Family | CMOS | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status - not confirmed in provided data] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 레벨 | [DATA_NEEDED: MSL level] | — |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |