EP910LC-30Y vs EP910LC-32 비교
다음의 상세 나란히 비교: EP910LC-30Y 제조: Altera 및 EP910LC-32 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910LC-30Y | EP910LC-32 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $25.40 | $9.85 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| 공급 전압 | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 패키지 | PLCC-44 | PLCC-32 |
| 동작 온도 | Commercial 0C to +70C | — |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| 실장 유형 | Surface Mount (PLCC socket) | Surface Mount (PLCC socket or direct solder) |
| RoHS 상태 | [DATA_NEEDED: RoHS status not specified in retrieved data] | unknown |
| Device Family | — | Altera Classic EPLD |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | 900 gates (typical) |
| Number of Dedicated Inputs | — | 10 |
| Number of I/O Pins | — | 20 |
| Speed Grade | — | -32 |
| Maximum Toggle Frequency (fMAX) | — | [DATA_NEEDED: fMAX value in MHz for -32 grade] |
| Pin-to-Pin Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns for -32 grade] |
| Supply Voltage (VCC) | — | 5 V |
| Logic Family | — | Low-power CMOS (LC suffix) |
| Programming Method | — | UV-erasable or one-time programmable (OTP for LC windowless variant) |
| 동작 온도 범위 | — | [DATA_NEEDED: commercial or industrial grade] |
| I/O Standard | — | TTL-compatible |
| MSL 레벨 | — | unknown |