EP910LC-35H vs EP910DC-35 비교
다음의 상세 나란히 비교: EP910LC-35H 제조: Altera 및 EP910DC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910LC-35H | EP910DC-35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $25.00 | $10.95 |
| Family | Classic EPLD (EP910) | Classic EPLD EP910 |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | 35 ns |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| 패키지 | 40-pin Ceramic DIP (H suffix) | 40-pin CDIP (Ceramic DIP) with quartz window |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | 12 |
| 동작 온도 | [DATA_NEEDED: operating temperature range grade] | 0 °C to +70 °C (commercial) |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | JEDEC fuse map via device programmer; UV erase |
| Logic Levels | TTL compatible | — |
| 대기 전류 | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| 실장 유형 | Through-hole (Ceramic DIP) | — |
| RoHS 상태 | unknown | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | Obsolete / last-time-buy from authorized distributors |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| 최대 클록 주파수 | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |