EP910LC44 vs EP910LC44-30T 비교

다음의 상세 나란히 비교: EP910LC44 제조: Altera 및 EP910LC44-30T 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP910LC44 EP910LC44-30T
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 최종 구매 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $8.95 $9.75
Product Family Classic EPLD (EP910 Series) —
Manufacturer Altera Corporation (now Intel PSG) —
Device Type Erasable Programmable Logic Device (EPLD) —
Macrocells 24 24
Total Product Terms 240 —
Dedicated Inputs 12 12
I/O Pins 24 —
Total Input Pins 36 (12 dedicated + 24 I/O as inputs) —
Global Clock Inputs 2 —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (nominal 5 V)
Propagation Delay (LC grade) [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] —
Propagation Delay (LC-30 grade) 33 ns (per EP910LC44-30 verified data) —
Process Technology CMOS —
패키지 44-pin PLCC (J-leaded) PQCC-44 (Plastic Leaded Chip Carrier, J-bend)
동작 온도 [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] —
Programming Method EPROM (erasable UV for ceramic; OTP for plastic PLCC) —
Architecture AND-OR sum-of-products with programmable macrocell feedback —
Logic Compatibility TTL-compatible CMOS I/O —
RoHS 상태 [DATA_NEEDED: not stated in verified data] —
Device Family — Classic EPLD
Logic Type — PAL-type CMOS EPLD (OT PLD)
Product Terms — 240
Propagation Delay (tPD) — 33 ns
I/O Lines — 24 (bidirectional)
Total Inputs — 36
Total Outputs — 24
External Clock Inputs — 2
Programming Technology — CMOS, UV-erasable (windowed package in family)
Security Bit — Programmable (logic readback protection)
Operating Temperature Grade — Commercial
Terminal Form — J-BEND
Package Code — QCCJ
실장 유형 — Surface Mount

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