EPC16UC88 vs EPC16UC88T 비교
다음의 상세 나란히 비교: EPC16UC88 제조: Altera 및 EPC16UC88T 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPC16UC88 | EPC16UC88T |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | Memory ICs | EEPROM |
| 수명 주기 상태 | Unknown | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $0.00 | $9.95 |
| Device Type | In-system programmable configuration PROM for FPGAs | — |
| Configuration Memory Capacity | 16 Mb | — |
| 공급 전압 | 3.3 V core and I/O | — |
| 패키지 | 88-UBGA (11x8) | 88-ball UBGA, 11 mm x 8 mm |
| Package Family | UBGA | — |
| In-System Programmability | IEEE Std. 1532 compatible | — |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | — |
| JTAG Boundary Scan | Supported | — |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | — |
| Configuration Architecture | Configuration controller and flash memory | — |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | — |
| Data Output | Configuration data output controlled by OE and nCS | — |
| Output Control | OE and nCS control tri-state buffer and address counter | — |
| 실장 유형 | Surface mount | — |
| Package Dimensions | 11 mm x 8 mm | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| 동작 온도 | [DATA_NEEDED: operating temperature] | — |
| Output Current | [DATA_NEEDED: output current] | — |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| 메모리 유형 | — | Non-volatile Flash configuration PROM (in-system programmable) |
| Memory Density | — | 16 Mbit (2,097,152 x 8 bits) |
| Configuration Interface | — | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF_DONE) |
| Maximum DCLK Frequency | — | 33 MHz |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| 동작 온도 범위 | — | -40 C to +85 C (industrial) |
| In-System Programming | — | IEEE Std 1149.1 (JTAG) |
| Cascade Support | — | Yes (for higher density multi-PROM chains) |
| MSEL Compatibility | — | FPP / PS configuration modes (3.3 V legacy) |
| Compatible FPGA Families | — | Cyclone, Cyclone II, Stratix, Stratix II, Stratix III, Stratix IV, Arria GX |
| Family Density Step | — | Largest member of EPC4 / EPC8 / EPC16 family |
| MSL 레벨 | — | [DATA_NEEDED: MSL] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |
| Open-Drain nINIT_CONF_DONE | — | Yes |