EPF10K100EQC208-2X vs EPF10K100EQC208-1N 비교
다음의 상세 나란히 비교: EPF10K100EQC208-2X 제조: Altera 및 EPF10K100EQC208-1N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPF10K100EQC208-2X - FLEX 10KE FPGA, 100K Gates, 208-PQFP | Altera
EPF10K100EQC208-2X ⚠ 최종 구매Intel
EPF10K100EQC208-1N - 100K Gate FLEX-10KE FPGA, 147 I/O, 208-PQFP | Intel
EPF10K100EQC208-1N ⚠ 최종 구매사양 비교
| 파라미터 | EPF10K100EQC208-2X | EPF10K100EQC208-1N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $59.50 | $54.90 |
| Series | FLEX-10KE | FLEX-10KE |
| Family | FLEX 10KE | FLEX 10K (SRAM-based FPGA with EAB) |
| Logic Elements / Cells | 4,992 | — |
| System Gates | 100,000 | — |
| Embedded Memory (EAB RAM) | 49,152 bits | — |
| Number of I/O Pins | 147 | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 624 |
| Number of Embedded Array Blocks (EABs) | 12 | — |
| Supply Voltage (VCCINT) | 2.375 V to 2.625 V (2.5 V nominal) | — |
| Process Technology | 0.22 µm SRAM | 0.42 um CMOS SRAM |
| Maximum Internal Frequency (-2 grade) | 250 MHz | — |
| 패키지 / 케이스 | 208-BFQFP (PQFP) | 208-BFQFP / 208-PQFP |
| Supplier Device Package | 208-PQFP (28 × 28 mm, 0.5 mm pitch) | 208-PQFP (28 x 28 mm) |
| Operating Temperature Grade | Commercial | — |
| Configuration Mode | Passive Serial / Passive Parallel Async | — |
| 실장 유형 | Surface Mount | Surface Mount |
| Lead-Free Plating (-X suffix) | Yes (matte-tin, lead-free) | — |
| RoHS 상태 | Compliant (-X suffix) | Compliant (lead-free, 'N' suffix) |
| MSL 레벨 | [DATA_NEEDED: MSL level] | — |
| Typical Gates | — | 100,000 gates |
| Logic Elements | — | 4,992 |
| Total RAM Bits | — | 49,152 bits |
| User I/Os | — | 147 |
| Supply Voltage - Core (VCCINT) | — | 2.375 V to 2.625 V |
| Propagation Delay (max) | — | 0.6 ns |
| Speed Grade | — | -1 (faster bin) |
| 동작 온도 | — | 0 C to +70 C (Commercial) |
| Configuration Method | — | SRAM, serial or parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |