EPF10K50EFC484-2 vs EPF10K100EFC484-3 비교
다음의 상세 나란히 비교: EPF10K50EFC484-2 제조: Altera 및 EPF10K100EFC484-3 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPF10K50EFC484-2 - 50K Gates FLEX-10KE FPGA, 484-BGA | Intel / Altera
EPF10K50EFC484-2 Obsolete사양 비교
| 파라미터 | EPF10K50EFC484-2 | EPF10K100EFC484-3 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $52.75 | $65.00 |
| Family | FLEX-10KE | FLEX 10KE |
| Logic Elements (LEs) | 2,880 | — |
| Typical Gates | 50,000 | 100,000 |
| Embedded Memory (Bits) | 40,960 | — |
| Embedded Array Blocks (EABs) | 12 (each 2,048 bits) | — |
| Maximum User I/O Pins | 220 | — |
| 패키지 | 484-ball FineLine BGA (FBGA) | 484-ball FineLine BGA |
| Process Technology | 0.22 micrometer CMOS | — |
| Core Voltage | 2.5 V | 2.5 V |
| Internal Frequency | 200 MHz | — |
| Speed Grade | -2 | -3 (fastest commercial) |
| 동작 온도 | 0 C to +70 C (Commercial) | 0C to +70C (Commercial) |
| JTAG Boundary-Scan | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 at 33/66 MHz (3.3 V); 5.0 V at speed grade -1 | — |
| 실장 유형 | Surface Mount (BGA) | — |
| Maximum System Gates | — | 158,000 |
| Logic Elements | — | 4,992 |
| Logic Array Blocks (LABs) | — | 624 |
| Embedded Memory (EAB RAM) | — | 49,152 bits |
| User I/O Pins | — | 338 |
| I/O Standards Supported | — | 2.5V / 3.3V / 5.0V (PCI-compliant) |
| JTAG Support | — | IEEE Std. 1149.1-1990 BST |
| Configuration Method | — | SRAM (volatile, requires configuration device) |
| RoHS 상태 | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |