EPF8820ARC208-3N vs EPF8820ARC208-3 비교
다음의 상세 나란히 비교: EPF8820ARC208-3N 제조: Altera 및 EPF8820ARC208-3 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPF8820ARC208-3N - FLEX 8000 FPGA, 672 LEs, 125MHz, 208-RQFP | Altera
EPF8820ARC208-3N ObsoleteIntel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 Obsolete사양 비교
| 파라미터 | EPF8820ARC208-3N | EPF8820ARC208-3 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $85.00 | $62.00 |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Usable Gates | 8,000 | 8,000 |
| Logic Elements | 672 | — |
| Logic Array Blocks (LABs) | 672 / 10 ≈ 67 LABs | — |
| FlipFlops | 152 | — |
| Maximum Operating Frequency | 125 MHz | 125 MHz |
| Propagation Delay | 5 ns (speed grade -3) | — |
| Process Technology | 0.42 µm CMOS | 0.42 µm CMOS |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Voltage | 3.3 V or 5 V (selectable) | — |
| User I/O Count | 152 | — |
| 패키지 | 208-pin RQFP / BFQFP Exposed Pad (28x28 mm) | — |
| Configuration Memory | SRAM (volatile, external configuration device required) | SRAM (volatile) |
| Configuration Devices | EPC1, EPC1213, EPC1064, EPC1441 | — |
| In-System Reconfigurability | Yes (ICR via configuration device or controller) | — |
| JTAG Support | Yes (boundary-scan + configuration) | — |
| Speed Grade | -3 | — |
| RoHS 상태 | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 8000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| 패키지 / 케이스 | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| 실장 유형 | — | Surface Mount |
| Packaging | — | Tray |
| 동작 온도 범위 | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |