EPM3064AT100-10N vs EPM3064ATC100-10NA 비교
다음의 상세 나란히 비교: EPM3064AT100-10N 제조: Altera 및 EPM3064ATC100-10NA 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Intel
EPM3064ATC100-10NA - MAX 3000A CPLD, 64 Macrocells, 10ns, TQFP-100 | Intel (Altera)
EPM3064ATC100-10NA ✓ 활성사양 비교
| 파라미터 | EPM3064AT100-10N | EPM3064ATC100-10NA |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $5.45 | $4.65 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 66 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Bank Voltage | 3.3 V | — |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | — |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | — |
| 패키지 | TQFP-100 (T100), 14 mm x 14 mm | TQFP-100 (0.5 mm pitch) |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| User I/Os | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX in MHz] |
| MultiVolt I/O Voltages | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| 동작 온도 | — | 0C to +70C (commercial) |
| Lead-Free / RoHS | — | Yes (NA suffix) |