EPM3064ATC100-7 vs EPM3064ATC100-10N 비교
다음의 상세 나란히 비교: EPM3064ATC100-7 제조: Altera 및 EPM3064ATC100-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 Obsolete사양 비교
| 파라미터 | EPM3064ATC100-7 | EPM3064ATC100-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $3.08 | $2.43 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 1,250 | 1,250 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 2 |
| Maximum User I/Os | 66 (in 100-pin TQFP) | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Maximum Internal Counter Frequency | 135.1 MHz | — |
| Supply Voltage - VCCINT (Core) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Technology | CMOS EEPROM | — |
| 패키지 | 100-pin TQFP | 100-pin TQFP |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| In-System Programming (ISP) | Yes, via IEEE 1149.1 JTAG | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| JTAG Boundary Scan | Yes | — |
| Lead Free / RoHS | Compliant (modern shipments) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| In-System Programmability | — | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |
| RoHS 상태 | — | Compliant (lead-free) |