EPM3256AFC256-7 vs EPM3512AFC256-18 비교
다음의 상세 나란히 비교: EPM3256AFC256-7 제조: Altera 및 EPM3512AFC256-18 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 Obsolete사양 비교
| 파라미터 | EPM3256AFC256-7 | EPM3512AFC256-18 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $12.10 | $17.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 256 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | — |
| User I/Os | 161 | — |
| Pin-to-Pin Logic Delay | 4.5 ns (max) | — |
| Counter Frequency | 227.3 MHz (max) | — |
| Propagation Delay (tpd) | 10 ns | — |
| Core Voltage | 3.3 V | — |
| I/O Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | — |
| Process Technology | CMOS EEPROM, 0.30 µm | — |
| In-System Programmability | IEEE Std. 1532-compliant 3.3-V ISP | — |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | — |
| 패키지 | FBGA-256 (FineLine BGA), 256 balls | 256-ball FineLine BGA (FCBGA) |
| 동작 온도 | 0 °C to 70 °C (Commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Speed Grade | -7 | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not specified in retrieved data] |
| Macrocells | — | 512 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD1) | — | 18 ns |
| Global Clock Networks | — | 4 |
| VCCINT (Core Supply) | — | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | — | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | — | 1.0 mm |
| 실장 유형 | — | Surface Mount |