EPM3512AFC256-18 vs EPM3512AFC256-20 비교
다음의 상세 나란히 비교: EPM3512AFC256-18 제조: Altera 및 EPM3512AFC256-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoleteAltera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 Obsolete사양 비교
| 파라미터 | EPM3512AFC256-18 | EPM3512AFC256-20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $17.20 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD1) | 18 ns | — |
| Global Clock Networks | 4 | — |
| VCCINT (Core Supply) | 3.0 V to 3.6 V (3.3 V typical) | — |
| VCCIO (I/O Supply) | 2.5 V or 3.3 V (MultiVolt) | — |
| 동작 온도 | [DATA_NEEDED: industrial/commercial grade] | [DATA_NEEDED: operating temperature range] |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) | — |
| 패키지 | 256-ball FineLine BGA (FCBGA) | 256-ball FBGA (Fine-pitch BGA) |
| Ball Pitch | 1.0 mm | — |
| RoHS 상태 | [DATA_NEEDED: not specified in retrieved data] | [DATA_NEEDED: RoHS compliance status] |
| 실장 유형 | Surface Mount | Surface Mount |
| Typical Usable Gates | — | 10,000 |
| Speed Grade | — | -20 (20 ns tPD) |
| 핀 수 | — | 256 |
| Operating Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| JTAG Support | — | Yes (boundary-scan + ISP) |
| MSL 레벨 | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| Configuration Memory | — | Internal EEPROM |