EPM3512AQC208-10-10N vs EPM3512AQC208-15N 비교
다음의 상세 나란히 비교: EPM3512AQC208-10-10N 제조: Altera 및 EPM3512AQC208-15N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N Obsolete사양 비교
| 파라미터 | EPM3512AQC208-10-10N | EPM3512AQC208-15N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $31.20 | $20.50 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | — |
| User I/Os | 172 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fCNT) | 87 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | 2.5 V / 3.3 V (MultiVolt) |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan (JTAG) | Yes, IEEE 1149.1 | — |
| PCI-SIG Compliance | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) | — |
| 동작 온도 | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| 패키지 | 208-pin PQFP (Plastic Quad Flat Pack) | PQFP-208 (QC208) |
| 실장 유형 | Surface Mount | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status] | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macro Cells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 172 |
| Typical Usable Gates | — | 12,000 |
| Number of Logic Elements | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Operating Supply Voltage (VCCINT) | — | 3.3 V |
| Programmable I/O Standards | — | LVTTL, LVCMOS, PCI (with external resistor) |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Support | — | Yes (BST/Boundary-Scan Test) |
| RoHS 상태 | — | [DATA_NEEDED: RoHS status] |