EPM5016DC-20 vs EPM5032DC-2 비교

다음의 상세 나란히 비교: EPM5016DC-20 제조: Altera 및 EPM5032DC-2 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5016DC-20 EPM5032DC-2
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $16.50 $8.75
Family MAX 5000 —
Device Type EPLD (UV-Erasable Programmable Logic Device) —
Macrocells 16 32
Product Terms 160 —
Dedicated Inputs 7 —
I/O Pins 8 —
Propagation Delay (tPD) 20 ns —
최대 클록 주파수 62.5 MHz —
Maximum Supply Voltage 5.25 V —
Nominal Supply Voltage 5.0 V —
Process Technology CMOS, UV-erasable —
Architecture PAL-type macrocell with Programmable Interconnect Array (PIA) —
Package Type 20-pin Ceramic DIP (Cerdip) with UV window —
Package Suffix Code DC = Ceramic DIP, Commercial —
Speed Grade -20 = 20 ns tPD -2 (tPD ~25 ns, commercial)
동작 온도 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial grade)
Programming Method UV erase + EPROM-style programming via Altera programming hardware —
RoHS 상태 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS]
Product Type — CPLD (Complex Programmable Logic Device)
Series — MAX 5000
Usable Gates (typical) — 600
Logic Array Blocks (LABs) — 4
패키지 — 20-pin CDIP (Ceramic DIP)
Configuration Memory — EPROM (one-time programmable per generation; UV-erasable variants exist)
Supply Voltage (VCC) — 5 V (single supply, +/-5%)
Programmable Pins / I/O — 20 pins (JEDEC-standard 0.300" ceramic DIP)
Programming Interface — Altera ByteBlaster / parallel-port JTAG-style ISP
Interconnect — Programmable Interconnect Array (PIA) with deterministic timing
실장 유형 — Through-Hole (DIP)
MSL 레벨 — Not applicable (through-hole hermetic ceramic)

데이터시트 & 자료

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