EPM5064LC-1 vs EPM5064JC-2 비교
다음의 상세 나란히 비교: EPM5064LC-1 제조: Altera 및 EPM5064JC-2 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5064LC-1 | EPM5064JC-2 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.95 | $23.10 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1.25K (approx.) | 1250 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (4.75 V to 5.25 V) |
| Internal Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Input Lines | 36 | — |
| Dedicated Inputs | 7 | 7 |
| Output Lines | 28 | — |
| Programming Technology | OTP / UV-Erasable EPROM | — |
| 패키지 | 44-pin PLCC (Plastic Leaded Chip Carrier) | 28-pin CLCC (J-lead, ceramic, windowed) |
| Process Technology | CMOS | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial or industrial grade] |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| I/O Pins | — | 28 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV-erase + EPROM programmer (not ISP) |
| Compliance | — | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |