EPM5192AGC-15 vs EPM5192AGC 비교

다음의 상세 나란히 비교: EPM5192AGC-15 제조: Altera 및 EPM5192AGC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192AGC-15 EPM5192AGC
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $27.80 $56.00
Product Type EPLD (Erasable Programmable Logic Device) —
Series MAX 5000 —
Macrocells 192 192
Logic Array Blocks 16 (typical for 192-macrocell MAX 5000) —
Maximum User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs 72 —
Propagation Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Supply Voltage (VCC) 5 V —
Technology CMOS, UV-erasable EPROM —
패키지 Ceramic Pin Grid Array (PGA) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
Programming Method UV erase + EPROM program (via Altera programmer) —
동작 온도 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
RoHS 상태 [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
수명 주기 상태 Obsolete / Last Time Buy (per Altera legacy product list) —
Family — MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Device Type — UV-Erasable / OTP Complex PLD (EPLD)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
공급 전압 — [DATA_NEEDED: VCC nominal and tolerance]
실장 유형 — Through-hole (Pin Grid Array)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

데이터시트 & 자료

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