EPM5192AJC84-20 vs EPM5192AJM84-20 비교
다음의 상세 나란히 비교: EPM5192AJC84-20 제조: Altera 및 EPM5192AJM84-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete
사양 비교
| 파라미터 | EPM5192AJC84-20 | EPM5192AJM84-20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $19.20 | $171.00 |
| Family | MAX 5000 | — |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | CMOS UV-Erasable/OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| 최대 클록 주파수 | 66.7 MHz | 66.7 MHz |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS EPROM (UV-erasable) |
| 패키지 | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin CQFP (S-CQCC-J84, J-lead) |
| Operating Temperature Grade | Commercial | — |
| 실장 유형 | Surface Mount (J-Lead) | — |
| MSL 레벨 | [DATA_NEEDED: MSL level] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | MAX 5000 (EPM5192) |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| Propagation Delay (tPD) | — | 33 ns (speed grade -20) |
| Terminal Form | — | J-Bend |
| Temperature Grade | — | MILITARY |
| Erasure Method | — | UV (quartz-windowed CQFP) or OTP |