EPM5192C-2 vs EPM5192GC-2 비교
다음의 상세 나란히 비교: EPM5192C-2 제조: Altera 및 EPM5192GC-2 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192C-2 | EPM5192GC-2 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $13.20 | $92.00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (PIA, typical) | 45 ns | — |
| Maximum Operating Frequency | 50 MHz | — |
| Process Technology | CMOS | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -2 | -2 |
| Programming Interface | JTAG / Altera MAX+ programming | — |
| RoHS 상태 | unknown | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Lead-Free | unknown | — |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Propagation Delay (tPD) | — | 12 ns typical (-2 grade) |
| Counter Frequency | — | 100 MHz minimum |
| Supply Voltage (VCC) | — | 5 V nominal |
| Technology | — | CMOS EPROM |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| 동작 온도 | — | Commercial (0C to +70C) |
| 실장 유형 | — | Through-hole (PGA socket) |