EPM5192IC-1 vs EPM5192LI-1 비교

다음의 상세 나란히 비교: EPM5192IC-1 제조: Altera 및 EPM5192LI-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192IC-1 EPM5192LI-1
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $13.95 $16.40
Family MAX 5000 EPLD MAX 5000
Macrocells 192 192
Usable Gates 3750 3,750
Dedicated Inputs 7 —
I/O Pins 64 —
Pin-to-Pin Delay (tPD) 15 ns (max, -1 speed grade) —
Counter Frequency (fCNT) 76.9 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (nominal 5 V) —
동작 온도 -40C to +85C (industrial) [DATA_NEEDED: industrial vs military range]
Technology CMOS, UV-erasable, in-system programmable —
패키지 68-pin ceramic J-lead (IC-1 suffix) —
Programming Interface JTAG / IEEE Std 1149.1 boundary scan —
Security Bit Yes (design protection) —
Supply Current (Icc, typical) [DATA_NEEDED: Icc] mA —
Output Drive Current (IOH/IOL) [DATA_NEEDED: IOH/IOL] mA —
Device Type — EPLD (UV-Erasable/OTP Complex PLD)
Maximum Toggle Frequency — 40 MHz
공급 전압 — 5 V
Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns at -1 grade]
User I/O Pins — [DATA_NEEDED: user I/O count for JLCC variant]
Package Type — JLCC (windowed, ceramic, UV-erasable)
Process Technology — CMOS EPROM, UV-erasable
Speed Grade — -1
핀 수 — [DATA_NEEDED: pin count of LI package]
실장 유형 — Surface Mount (JLCC with J-leads)
MSL 레벨 — [DATA_NEEDED: MSL level]
RoHS 상태 — [DATA_NEEDED: RoHS status of ceramic LI variant]
Lead Free — [DATA_NEEDED: lead-free]
Programmable Interconnect — Programmable Interconnect Array (PIA)
Architecture — EEPROM/EPROM-based, non-volatile, instant-on

데이터시트 & 자료

모든 제품 보기 BOM 생성 견적 요청