EPM5192JC68 vs EPM5192JC1 비교
다음의 상세 나란히 비교: EPM5192JC68 제조: Altera 및 EPM5192JC1 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192JC68 | EPM5192JC1 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $15.85 | $48.30 |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Elements / Macrocells | 192 macrocells | — |
| User I/O Pins | 76 | — |
| 핀 수 | 68 | — |
| Package Type | PLCC-68 (J-Lead) | — |
| 동작 온도 | 0C to 70C (commercial, JC suffix) | [DATA_NEEDED: operating temp range] |
| 공급 전압 | [DATA_NEEDED: VCC] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Programmable Interconnect | Programmable Logic Array + Macrocells | — |
| Dedicated Inputs | 12 | — |
| Clock Pins | 4 dedicated | — |
| 실장 유형 | Surface Mount (PLCC socket compatible) | [DATA_NEEDED: surface mount or through-hole] |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | unknown |
| Programming Tool | MAX+PLUS II (legacy) | — |
| Family | — | MAX 5000 (MAX 5xxx CPLD) |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Macro Cells | — | 192 |
| Usable Gates | — | 3750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Process Technology | — | 0.5 µm CMOS, UV-erasable EPROM |
| Propagation Delay (typ) | — | [DATA_NEEDED: propagation delay in ns] |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| 패키지 | — | [DATA_NEEDED: exact package from datasheet] |
| Programming Interface | — | JTAG-compatible (Altera MAX 5xxx) |
| Logic Blocks (LABs) | — | 24 (8 macrocells per LAB) |
| AEC-Q100 | — | not_applicable |
| Lifecycle | — | Obsolete - last-time-buy stock only at franchised distributors |