EPM7256SQC208-7N vs EPM7256SRC208-10N 비교
다음의 상세 나란히 비교: EPM7256SQC208-7N 제조: Altera 및 EPM7256SRC208-10N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM7256SQC208-7N | EPM7256SRC208-10N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $27.20 | $27.20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 164 | 164 |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | EEPROM (non-volatile) |
| 패키지 | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | Commercial (0C to +70C) | 0C to +70C (commercial) |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | — |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| RoHS 상태 | Compliant (N suffix = lead-free) | Compliant (N suffix = lead-free) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns |
| Open-Drain Output | Optional per I/O pin | — |
| Maximum Counter Frequency | — | 100 MHz |
| 공급 전압 | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Logic Levels | — | 5.0 V TTL/CMOS compatible |
| Number of Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Maximum User Flash Memory | — | [DATA_NEEDED: user flash memory] |