EPM9400LC84-15 vs EPM9320LC84-10 비교

다음의 상세 나란히 비교: EPM9400LC84-15 제조: Altera 및 EPM9320LC84-10 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM9400LC84-15 EPM9320LC84-10
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $23.10 $84.96
Family MAX 9000 MAX 9000 EPLD
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 8,000 6000 (typical)
Macro Cells 400 —
Logic Array Blocks 25 —
Maximum User I/Os 59 —
Maximum Operating Frequency 117.6 MHz —
Speed Grade -15 (15 ns pin-to-pin delay) —
Core Supply Voltage (VCCINT) 5.0 V —
Input Logic Compatibility TTL, 3.3 V and 5.0 V tolerant —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE Std. 1149.1 compliant (ISP) —
패키지 84-pin PLCC 84-pin PLCC (JEDEC MO-047)
실장 유형 Surface Mount Surface Mount (PLCC socket also common)
동작 온도 0C to +70C (Commercial) 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix]
Minimum VCCINT 4.75 V —
Programming Method In-System Programmable via JTAG —
RoHS 상태 [DATA_NEEDED: RoHS status] ROHS3 Compliant (per fpgalink listing)
Device — EPM9320
Macrocells — 320
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 168 (varies by package)
Pin-to-Pin Logic Delay (tPD) — 10 ns
Maximum Frequency (fCNT) — [DATA_NEEDED: fCNT in MHz]
Supply Voltage (VCC) — 5.0 V (typical, see datasheet)
Process Technology — 0.7 µm CMOS EEPROM/UV-EPROM
Programming Interface — JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible
Configuration — Non-volatile EEPROM (instant-on, no boot PROM)
습도 민감도 레벨 (MSL) — MSL-3, 168 hours (per fpgalink listing)
Manufacturer Lead Time — 1-7 days (per fpgalink listing)

데이터시트 & 자료

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