EPM9560GC280-15 vs EPM9560GC280-20 비교
다음의 상세 나란히 비교: EPM9560GC280-15 제조: Altera 및 EPM9560GC280-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete사양 비교
| 파라미터 | EPM9560GC280-15 | EPM9560GC280-20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $115.00 | $360.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 560 | — |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| 실장 유형 | Through-Hole | Through-Hole (CPGA socket) |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| RoHS 상태 | Non-compliant (ceramic CPGA, contains lead) | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] |
| 수명 주기 상태 | Obsolete (legacy Altera MAX 9000 family) | — |
| Usable Gates | — | 12,000 |
| Macrocells | — | 560 |
| Maximum User I/O | — | 212 |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Counter Frequency (max) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage | — | 3.3 V or 5.0 V configurable |
| Process Technology | — | CMOS EEPROM |
| 패키지 | — | 280-pin CPGA (Ceramic Pin Grid Array) |
| 동작 온도 | — | [DATA_NEEDED: commercial/industrial/military grade] |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG |