EPM9560GC280-15 vs EPM9560GC280-20 Comparison

Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560GC280-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-15 EPM9560GC280-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type EE PLD (CMOS EEPROM-based CPLD) CPLD (Complex Programmable Logic Device)
Macro Cells 560 —
Typical Gates 12,000 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns (speed grade -15) —
Propagation Delay (alternate datasheet figure) 16.6 ns —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Operating Temperature (Commercial) 0C to +70C —
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) —
Mounting Type Through-Hole Through-Hole (CPGA socket)
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 —
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) —
Architecture Multiple Array MatriX (MAX) —
RoHS Status Non-compliant (ceramic CPGA, contains lead) [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant]
Lifecycle Status Obsolete (legacy Altera MAX 9000 family) —
Usable Gates — 12,000
Macrocells — 560
Maximum User I/O — 212
Pin-to-Pin Delay — 20 ns (speed grade -20)
Counter Frequency (max) — 100 MHz
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
I/O Voltage — 3.3 V or 5.0 V configurable
Process Technology — CMOS EEPROM
Package — 280-pin CPGA (Ceramic Pin Grid Array)
Operating Temperature — [DATA_NEEDED: commercial/industrial/military grade]
In-System Programming — Yes, via IEEE 1149.1 JTAG

Datasheets & Resources

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