MX574ALEWI+TCDR vs MC145572PBR2 비교
다음의 상세 나란히 비교: MX574ALEWI+TCDR 제조: Analog Devices 및 MC145572PBR2 제조: NXP Semiconductors. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Analog Devices
MX574ALEWI+TCDR - 12-Bit 25µs SAR ADC, 28-SOIC | Maxim Integrated
MX574ALEWI+TCDR ✓ 활성NXP Semiconductors
MC145572PBR2 - ISDN U-Interface Transceiver | NXP | 44-LQFP
MC145572PBR2 Obsolete사양 비교
| 파라미터 | MX574ALEWI+TCDR | MC145572PBR2 |
|---|---|---|
| 브랜드 | Analog Devices | NXP Semiconductors |
| 카테고리 | ADC/DAC | Interface ICs |
| 수명 주기 상태 | 활성 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $17.10 | $5.20 |
| Manufacturer | Analog Devices Inc. (formerly Maxim Integrated) | NXP Semiconductors (formerly Freescale / Motorola) |
| MPN | MX574ALEWI+TCDR | — |
| Converter Type | SAR (Successive Approximation Register) ADC | — |
| 분해능 | 12 bit | — |
| Number of Inputs | 1 | — |
| Input Type | Single-Ended (unipolar or bipolar ranges via pin strapping) | — |
| Maximum Conversion Time | 25 µs | — |
| Sample Rate (max) | 40 kSPS (typ) | — |
| Analog Input Ranges | 0 to +5 V, 0 to +10 V, ±5 V, ±10 V (software/strap-selectable) | — |
| Internal Reference | +10 V buried Zener, ±0.25 % initial accuracy (typ) | — |
| Data Interface | 12-bit parallel, 8-bit parallel, or serial | — |
| 출력 유형 | Three-state (high-Z) CMOS-compatible | — |
| Integral Nonlinearity (A grade) | ±1 LSB (max) | — |
| Supply Voltages | V+ = +12 V or +15 V, V- = -12 V or -15 V, VCC (digital) = +5 V | — |
| Power Consumption | 150 mW (typ, ±15 V supply) | — |
| 동작 온도 | 0 °C to +70 °C (commercial, 'L' grade) | [DATA_NEEDED: operating temperature range] |
| 패키지 | 28-pin SOIC wide-body (SOIC-28W) | 44-LQFP (10x10 mm) |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | Compliant | RoHS non-compliant (SnPb finish, per legacy Freescale data) |
| AEC-Q100 | Not qualified (commercial grade) | — |
| Part Type | — | ISDN U-Interface Transceiver |
| 공급 전압 | — | 5 V (typical) |
| 데이터 속도 | — | 160 kbps (2B1Q full-duplex over single twisted pair) |
| Line Code | — | 2B1Q (ANSI T1.601-1992) |
| Interface Standard | — | ANSI T1.601-1992 / ETSI ETR 080 |
| Operating Modes | — | NT (Network Termination) and LT (Line Termination), strap-selectable |
| HDLC Controller | — | On-chip, up to 4x 16-bit or 2x 32-bit identifiers |
| Echo Canceller | — | Integrated adaptive |
| Scrambler/Descrambler | — | On-chip |
| Host Interface | — | Parallel microprocessor-compatible |
| Lead-Free Status | — | Contains lead (legacy PBR2 tape-and-reel part marking) |
| Series | — | MC145572 |
| Part Status | — | Obsolete / Last-time-buy stock only |