RTAX2000S-CG624PROTO vs RTAX2000S-1CG624PROTO 비교
다음의 상세 나란히 비교: RTAX2000S-CG624PROTO 제조: Microchip Technology 및 RTAX2000S-1CG624PROTO 제조: Microchip Technology. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Microchip Technology
RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX2000S-CG624PROTO ✓ 활성Microchip Technology
RTAX2000S-1CG624PROTO - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CG624PROTO ✓ 활성사양 비교
| 파라미터 | RTAX2000S-CG624PROTO | RTAX2000S-1CG624PROTO |
|---|---|---|
| 브랜드 | Microchip Technology | Microchip Technology |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $0.00 | $0.00 |
| Family | RTAX-S Radiation-Tolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| System Gates | 2,000,000 | — |
| Logic Cells (R-cells) | 21,504 | — |
| D-Flip-Flops (Registers) | 32,256 | — |
| Logic Architecture | CMOS antifuse (OTP), SEU-hardened | — |
| 패키지 | CCGA-624 (ceramic column grid array, 624 balls) | CCGA-624 (CG624 ceramic column grid array) |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Logic Family | CMOS | — |
| Configuration | Live at power-up (non-volatile antifuse) | Live at power-up (nonvolatile antifuse) |
| SEU Immunity | SEU rate < 10^-10 errors/bit-day (per family datasheet) | — |
| Prototyping Variant | Yes (PROTO suffix) | — |
| Embedded Memory | Embedded SRAM blocks (FIFO / dual-port capable) | 540 kbits (family max, with optional EDAC) |
| I/O Standards | Single-ended and differential (P/N pin pairs) | — |
| Design Software | Microsemi/Microchip Libero SoC | — |
| 공급 전압 | [DATA_NEEDED: core and I/O supply voltage] | — |
| Total Ionizing Dose (TID) | [DATA_NEEDED: TID rating in krad(Si)] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Maximum I/O Count (624-ball pkg) | [DATA_NEEDED: user I/O count] | — |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Equivalent System Gates | — | 2000000 |
| Logic Cells | — | 32256 |
| Configurable Logic Blocks (CLBs) | — | 21504 |
| User I/Os (family max) | — | 684 |
| Total Ionizing Dose (functional) | — | 300 krad (Si) |
| Total Ionizing Dose (parametric) | — | 200 krad (Si) |
| SEU Rate | — | Less than 1E-10 errors per bit-day |
| Maximum System Frequency | — | 350 MHz (family performance) |
| Technology | — | CMOS antifuse (one-time programmable) |
| Speed Grade | — | -1 |
| Qualification Flow | — | PROTO (engineering prototype) |