AD9235BRURL7-40 - 12-Bit 40 MSPS 3V ADC | Analog Devices
부품 번호: AD9235BRURL7-40 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.85 | $10,850.00 |
AD9235BRURL7-40 개요
A pipelined ADC is a multi-stage converter architecture that processes samples in parallel sub-stages, achieving high sampling rates while keeping per-stage power dissipation low. Pipelined ADCs, in the broader ADC hierarchy, sit between successive-approximation-register (SAR) converters and flash converters, combining moderate resolution (typically 8-16 bits) with high throughput (tens to hundreds of MSPS). They are widely used in communications, instrumentation, and imaging applications where speed and resolution must be balanced against power and cost.
Key features of the AD9235BRURL7-40 include a fully differential SHA input that supports user-selectable input ranges and offsets (single-ended or differential), an internal 2.5 V bandgap reference (external reference option available), CMOS-compatible digital outputs, and low power dissipation of approximately 110 mW at 40 MSPS with 3 V supply. The wide input bandwidth SHA handles multiplexed systems that switch full-scale voltage levels in successive channels and supports undersampling of IF signals well beyond the Nyquist rate. Operating temperature range spans -40°C to +85°C, making it suitable for industrial environments.
Typical applications include communications IF sampling, portable and battery-powered imaging systems, multichannel multiplexed data acquisition, handheld oscilloscope front-ends, and cable-modem downstream receivers. The on-chip reference and small TSSOP footprint reduce external BOM, enabling compact designs. When using the internal reference, decouple REFT and REFB pins with high-quality ceramic capacitors; for best SFDR in multitone IF applications, the external reference mode is recommended.
드롭인 대체품: AD9235BRURL7-40 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD9235BRURL7-40 (동일 폼 팩터 및 풋프린트) — 차이점: Reference, Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD9235BRUZ-40
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9235BRUZRL7-40
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9235BRURL7-65
✅ 드롭인✓ 재고 있음
$11.05 / 개
데이터시트 보기 →AD9235BRURL7-20
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
AD9235BRURL7-40 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| 샘플링 속도 | 40 MSPS |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| 공급 전압 | 2.7 V to 3.6 V (single 3 V supply) |
| Power Dissipation (typ @ 40 MSPS) | 110 mW (typical) |
| Input Type | Differential (SHA), single-ended capable |
| Input Range | 1 Vp-p differential (with 2 Vp-p option) |
| Reference | Internal 2.5 V or external |
| Digital Interface | Parallel CMOS, 12-bit |
| 동작 온도 | -40°C to +85°C |
| 패키지 | 28-TSSOP (4.40 mm body width) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant (RU package suffix) |
| Packaging | Tape & Reel (TR - R7) |
AD9235BRURL7-40 핀 구성
| 핀 1 | AIN — Analog input (positive) |
| 핀 2 | AINB — Complementary analog input |
| 핀 3 | VREF — Reference I/O (internal or external) |
| 핀 4 | SENSE — Reference mode select (input range) |
| 핀 5 | REFT — Reference top decoupling |
| 핀 6 | REFB — Reference bottom decoupling |
| 핀 7 | CML — Common-mode level output |
| 핀 8 | AVDD — Analog supply (3 V) |
| 핀 9 | AGND — Analog ground |
| 핀 10 | AVDD — Analog supply (3 V) |
| 핀 11 | CLK — Clock input |
| 핀 12 | CLKB — Complementary clock input (optional) |
| 핀 13 | DRVDD — Digital output driver supply (3 V) |
| 핀 14 | DRGND — Digital driver ground |
| 핀 15 | D0 — Data output bit 0 (LSB) |
| 핀 16 | D1 — Data output bit 1 |
| 핀 17 | D2 — Data output bit 2 |
| 핀 18 | D3 — Data output bit 3 |
| 핀 19 | D4 — Data output bit 4 |
| 핀 20 | D5 — Data output bit 5 |
| 핀 21 | D6 — Data output bit 6 |
| 핀 22 | D7 — Data output bit 7 |
| 핀 23 | D8 — Data output bit 8 |
| 핀 24 | D9 — Data output bit 9 |
| 핀 25 | D10 — Data output bit 10 |
| 핀 26 | D11 — Data output bit 11 (MSB) |
| 핀 27 | NC — Not connected (no internal bond) |
| 핀 28 | OTR — Out-of-range indicator output |
일반적인 애플리케이션
AD9235BRURL7-40 적합 용도: 6 애플리케이션s: Communications IF Sampling, Portable Imaging Systems, Multichannel Data Acquisition, Handheld Oscilloscope Front-End, Cable Modem Downstream Receiver, Ultrasound Imaging Receivers.
Communications IF Sampling
The AD9235BRURL7-40's 40 MSPS sampling with 12-bit resolution and differential 1 Vp-p SHA makes it ideal for IF undersampling in communications receivers. Its wide analog input bandwidth, exceeding Nyquist, allows direct sampling of intermediate frequencies that otherwise require mixers, simplifying receiver chain design. The on-chip duty-cycle stabilizer preserves SFDR performance even when the clock has non-50% duty. Power dissipation of 110 mW typical at 40 MSPS keeps thermal rise low in space-constrained multi-channel base stations. The single 3 V supply rails (AVDD/DRVDD) simplify distribution and reduce EMI compared to 5 V designs. Placed between an IF SAW filter and a digital demodulator/DSP, this ADC maintains high ENOB while enabling software-defined radio architectures.
추천
Portable Imaging Systems
Battery-powered camera, scanner, and handheld imager designs benefit from the AD9235BRURL7-40's 110 mW dissipation and single 3 V supply. The 12-bit resolution preserves image gradient detail, and the parallel CMOS output interfaces directly to ASICs/FPGAs without serializer overhead. The TSSOP-28 footprint enables compact PCB layouts where a 3 mm × 4.4 mm body matches handheld product enclosures. The internal reference removes external component cost, critical in price-sensitive consumer imaging equipment. Downsampling to 20 MSPS via lower clock rates further cuts dissipation for low-frame-rate medical, industrial, or scientific imaging. Operating temperature extends to +85°C, allowing outdoor point-and-shoot and industrial inspection deployments.
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Multichannel Data Acquisition
Multiplexed data-acquisition boards use the AD9235BRURL7-40 as a shared ADC across multiple analog input channels. Its wide-bandwidth, fully differential SHA settles accurately within one clock cycle after each multiplexed input switch, minimizing channel-to-channel crosstalk. The 28-TSSOP package simplifies board layout, supporting 4- or 8-channel simultaneous-sample boards with shared ADC + per-channel SHA front-ends. The 1 Vp-p differential input accepts direct thermocouple, strain-gauge, and transducer signals with proper signal conditioning. The industrial -40 to +85°C operating range covers factory-floor vibration and temperature stress.
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Handheld Oscilloscope Front-End
Compact digital oscilloscopes benefit from the AD9235BRURL7-40's 12-bit resolution and 40 MSPS throughput, providing enough bandwidth to capture 5-10 MHz signals with reasonable density per division. Its differential input structure tolerates probe-ground loop voltages, and the CMOS-parallel output allows direct capture into an FPGA buffer memory. The TSSOP-28 footprint accommodates small handheld form-factors where board area is scarce. Internal duty-cycle stabilizer compensates for non-50% clock from low-cost oscillators, simplifying BOM. Power scaling with clock rate allows firmware to lower dissipation during idle by gating the sample clock.
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Cable Modem Downstream Receiver
Downstream QAM/DOCSIS cable-modem receivers digitize IF or bandpass-split RF signals at high IF frequencies. The AD9235BRURL7-40's wideband SHA and 40 MSPS rate let designers undersample downstream carriers near 30-36 MHz while meeting 12-bit SFDR requirements. The internal voltage reference stabilizes ADC gain across temperature, important for long operating sessions in cable headend and consumer premises equipment. The 3 V single-supply design matches DOCSIS tuner requirements. Differential 1 Vp-p input accepts common DOCSIS front-end output levels without attenuation, removing an external amplifier stage.
추천
Ultrasound Imaging Receivers
Portable cart-based and handheld ultrasound imagers benefit from the AD9235BRURL7-40's low 110 mW dissipation and 12-bit resolution when digitizing time-gain-amplified echo signals. The wide input bandwidth supports the multi-MHz transducers required for high-frequency imaging. Multiple parallel ADC channels can share a clock distribution to maintain phase coherence across receive beams, with each AD9235BRURL7-40 capturing one channel's beamformed RF. Internal reference stabilizes gain across analog front-end gain controls. Industrial temperature range supports hospital, ambulance, and field-deployable diagnostic equipment.
추천
추천 제품 요약
엔지니어링 참조 데이터: AD9235BRURL7-40 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD9235BRUZ-40 | AD9235BRUZRL7-40 | AD9235BRURL7-65 | AD9235BRURL7-20 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-TSSOP (RU) | 28-TSSOP (RU) - same | 28-TSSOP (RU) - same | 28-TSSOP (RU) - same | 28-TSSOP (RU) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | 65 MSPS (+62%) | 20 MSPS (-50%) |
| Lead Finish | SnPb (non-Z suffix) | Pb-free matte-tin (RoHS) | Pb-free matte-tin (RoHS) | SnPb (non-Z) | SnPb (non-Z) |
| Packaging Medium | Tape & Reel (R7) | Tube | Tape & Reel (R7) | Tape & Reel (R7) | Tape & Reel (R7) |
| Lifecycle Status | Obsolete (last-time-buy) | Obsolete | Obsolete | Obsolete | Obsolete |
| Supply Voltage | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
주요 차별점
- Highest obsoleted-stock speed variant offered in TSSOP (vs AD9235BRURL7-65)
- SnPb lead finish supports legacy industrial/medical platforms (vs AD9235BRUZ-40)
- Tape-and-reel R7 suffix enables high-volume automation (vs AD9235BRUZ-40 (tube))
설계 노트
Estimated: at 3 V supply and 40 MSPS, the AD9235BRURL7-40 dissipates approximately 110 mW (per datasheet), drawing ~37 mA. Provide separate AVDD and DRVDD rails with independent ferrite beads and at least 0.1 µF + 10 µF ceramic bypass capacitors near each supply pin. For lowest noise, isolate DRVDD from AVDD through a ferrite to keep digital switching transients away from the sensitive analog front-end. A low-noise LDO (e.g., ADP3330) on AVDD significantly improves spurious performance versus a switching regulator.
Lay out the analog input traces as a 50 Ω matched differential pair routed symmetrically to the AIN and AINB pins. Keep digital output traces (D0-D11, OTR) routed together and away from the analog input section, ideally separated by a ground moat. Provide a solid uninterrupted analog ground plane beneath the SHA input network. Place the REFT and REFB decoupling capacitors as close to their respective pins as possible, using a small 0.1 µF ceramic. The TSSOP-28 thermal pad is not exposed and has a theta_JA in the 90-100 °C/W range, so no additional heatsinking is required at 110 mW dissipation.
Drive the CLK input with a clean, low-jitter source (e.g., 5 ps RMS or better for full ENOB performance). The on-chip duty-cycle stabilizer tolerates clock duty cycle from 30/70 to 70/30, allowing relaxation of the CLK driver spec. Terminate the input clock line with a 50 Ω resistor at the CLK pin. Use matched-length routing for the DDR/differential clock pair (if using CLKB) to maintain timing margin. For best SFDR in IF-sampling applications, bypass the duty-cycle stabilizer and provide an explicit 50% duty clock.
Do not exceed 3.6 V on AVDD/DRVDD: damage is permanent. Always operate with the REF bypass capacitors (REFT/REFB pins) populated; running with internal reference without external decoupling typically degrades SNR by 1-3 dB. The SENSE pin must be tied to a defined logic level (AVDD or AGLD) for the desired input range; floating SENSE causes indeterminate input range. When daisy-chaining clocks in multichannel applications, use a clock buffer (e.g., AD9516) rather than passive splitting to maintain duty and amplitude.
규정 준수 정보
Lead finish is SnPb (non-Z suffix), so the BRURL7-40 is non-RoHS; RoHS compliance requires the BRUZ variants. AEC-Q100 not applicable (analog signal path ADC, not safety-critical automotive qualified). Lifecycle status obsolete per DigiKey listing.
