AD9235BRURL7-65 - 12-Bit 65 MSPS ADC, 3V, TSSOP-28 | Analog Devices
부품 번호: AD9235BRURL7-65 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.05 | $11,050.00 |
AD9235BRURL7-65 개요
An ADC (analog-to-digital converter) is a semiconductor device that converts a continuous analog voltage into a discrete digital code at a sampling rate set by an external clock. Pipelined ADCs like the AD9235 use a multi-stage architecture that enables high sample rates at low power, while 12-bit resolution is the workhorse for cellular base stations, ultrasound imaging, and instrumentation. Within the broader taxonomy, the AD9235 sits in the data-converter category of mixed-signal ICs.
Key features of the AD9235BRURL7-65 include a differential analog input with 500 MHz bandwidth, an on-chip sample-and-hold amplifier (SHA), an internal voltage reference, and ±0.4 LSB differential non-linearity (DNL). The analog input range scales from 1 V p-p to 2 V p-p, output data is available in offset-binary or twos-complement format, and an integrated clock-duty-cycle stabilizer (DCS) relaxes clock-source requirements.
A proprietary front-end SHA driving the pipelined core allows IF-sampling well beyond the Nyquist limit, useful in undersampling radio receivers. Power consumption is 300 mW at 65 MSPS, and a flexible LVCMOS/TTL-compatible parallel digital interface simplifies FPGA/CPLD downstream connections.
Typical applications include communications IF sampling, ultrasound and medical imaging front-ends, low-cost instrumentation, and high-speed data acquisition cards. Designers value the part when a low-power, single-supply 12-bit ADC in a compact surface-mount footprint is needed.
When laying out the PCB, keep analog and digital grounds separated and join them at a single point near the ADC to limit return-path noise; place the input anti-alias filter as close as practical to the analog inputs and use a stable, low-jitter clock source to preserve SNR and SFDR.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and PCB-level design notes not found in the manufacturer datasheet, helping engineers select the right speed grade and validate second-source supply.
드롭인 대체품: AD9235BRURL7-65 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD9235BRURL7-65 (동일 폼 팩터 및 풋프린트) — 차이점: Reference, Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD9235BRUZRL7-65
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9235BRU-65
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9235BRURL7-40
✅ 드롭인✓ 재고 있음
$10.85 / 개
데이터시트 보기 →AD9235BRU-20
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9236BRUZ-80
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
AD9235BRURL7-65 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Number of Channels | 1 |
| Sampling Rate (Max) | 65 MSPS |
| Architecture | Pipelined |
| 공급 전압 | 3 V (2.7 V to 3.6 V) |
| Power Consumption | 300 mW at 65 MSPS |
| Analog Input Bandwidth | 500 MHz |
| Analog Input Range | 1 V p-p to 2 V p-p |
| Analog Input Type | Differential |
| SNR (to Nyquist, -1 dBFS) | 70 dBFS |
| SFDR (to Nyquist) | 85 dBFS |
| DNL | +/-0.4 LSB (typical) |
| Data Interface | Parallel (LVCMOS/TTL) |
| Output Format | Offset binary or twos complement |
| Reference | Internal (on-chip) |
| Clock Duty-Cycle Stabilizer | Yes (integrated) |
| 동작 온도 범위 | -40C to +85C |
| 패키지 | 28-TSSOP (4.40 mm body width) |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 1 (unlimited floor life) |
AD9235BRURL7-65 핀 구성
| 핀 1 | DVDD — Digital supply voltage (3 V) |
| 핀 2 | DGND — Digital ground |
| 핀 3 | CLOCK+ — Differential clock input, positive |
| 핀 4 | CLOCK- — Differential clock input, negative |
| 핀 5 | AIN- — Differential analog input, negative |
| 핀 6 | AIN+ — Differential analog input, positive |
| 핀 7 | VREF — Internal reference bypass / external reference input |
| 핀 8 | REFT — Internal reference top decoupling |
| 핀 9 | REFB — Internal reference bottom decoupling |
| 핀 10 | AVDD — Analog supply voltage (3 V) |
| 핀 11 | AGND — Analog ground |
| 핀 12 | CML — Common-mode level bypass (drive bias for analog inputs) |
| 핀 13 | AVDD2 — Analog supply (input buffer) |
| 핀 14 | AGND2 — Analog ground (input buffer) |
| 핀 15 | D11 (MSB) — Parallel data output, MSB |
| 핀 16 | D10 — Parallel data output |
| 핀 17 | D9 — Parallel data output |
| 핀 18 | D8 — Parallel data output |
| 핀 19 | D7 — Parallel data output |
| 핀 20 | D6 — Parallel data output |
| 핀 21 | D5 — Parallel data output |
| 핀 22 | D4 — Parallel data output |
| 핀 23 | D3 — Parallel data output |
| 핀 24 | D2 — Parallel data output |
| 핀 25 | D1 — Parallel data output |
| 핀 26 | D0 (LSB) — Parallel data output, LSB |
| 핀 27 | OTR — Out-of-range flag |
| 핀 28 | DCS/PD — Clock-duty-cycle stabilizer or power-down control |
일반적인 애플리케이션
AD9235BRURL7-65 적합 용도: 6 애플리케이션s: Communications IF Sampling Receiver, Medical Ultrasound Imaging Front-End, Portable Instrumentation and Data Acquisition, Low-Cost Multichannel Wireless Receiver, Industrial Process Control Measurement, Time-Interleaved or Multi-Board Baseband Recorder.
Communications IF Sampling Receiver
The AD9235BRURL7-65 is used in IF stages of cellular base-station receivers and microwave-link down-converters where the ADC samples a low-IF or zero-IF modulated carrier. Its 500 MHz analog input bandwidth and 65 MSPS sampling clock comfortably support IFs in the 25-100 MHz range, while the 70 dBFS SNR to Nyquist gives the back-end DSP >11 ENOB at oversampled baseband. Combined with a 3 V single supply and 300 mW dissipation, it cuts thermal load versus legacy 5 V ADCs, and the integrated clock-duty-cycle stabilizer relaxes jitter margin on TCXO-derived clocks.
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Medical Ultrasound Imaging Front-End
In ultrasound beamformers the AD9235BRURL7-65 digitizes the receive channel after TGC and LNA stages. The 12-bit resolution at 65 MSPS captures the dynamic range of returning echoes from deep tissue while keeping the LVCMOS parallel interface compatible with mid-range FPGAs. Its 300 mW dissipation lets designers stack 16-32 channels on a single board without exceeding thermal budgets. The integrated SHA and differential front-end reject common-mode pickup from piezo cables.
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Portable Instrumentation and Data Acquisition
Hand-held oscilloscope and field data-acquisition cards adopt the AD9235BRURL7-65 to deliver 12-bit precision at 65 MSPS on a single 3 V rail, ideal for battery-powered applications. The parallel output bus feeds directly into an FPGA or Cortex-M4-based MCU with DMA, while 1 V p-p to 2 V p-p range supports both legacy and modern sensor outputs. Low 300 mW dissipation enables fan-less mechanical designs suitable for IP-rated enclosures.
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Low-Cost Multichannel Wireless Receiver
Cost-sensitive wireless LNBs and broadband software-defined-radio dongles use the AD9235BRURL7-65 as the digital IF digitizer. Its 12-bit accuracy at 65 MSPS provides headroom for narrowband digital filtering, while the 28-TSSOP footprint enables dense PCB layouts behind multi-element antenna arrays. Internal reference removes external precision components, and the optional twos-complement output simplifies signed-math DSP pipelines.
추천
Industrial Process Control Measurement
Distributed control systems (DCS) and condition-monitoring vibration sensors use the AD9235BRURL7-65 to capture vibration and acoustic-emission waveforms in rotating machinery. Its 70 dBFS SNR preserves harmonic detail for FFT-based diagnostics, while the industrial -40C to +85C operating range matches factory-floor requirements. Single-supply 3 V simplifies integration into PLC modules powered from 24 V via a small point-of-load regulator.
추천
Time-Interleaved or Multi-Board Baseband Recorder
Multi-board data-acquisition chassis interleave multiple AD9235BRURL7-65 ADCs to reach sample rates from 130 MSPS to several hundred MSPS for radar baseband recorders and high-throughput test instruments. The closely matched analog front-end preserves channel-to-channel gain and offset alignment, while the wide 500 MHz input bandwidth eases design-in of anti-alias filtering. Synchronized via a shared low-jitter clock, the parallel outputs multiplex cleanly into high-density FPGAs.
추천
추천 제품 요약
엔지니어링 참조 데이터: AD9235BRURL7-65 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD9235BRUZRL7-65 | AD9235BRU-65 | AD9235BRURL7-40 | AD9235BRU-20 | AD9236BRUZ-80 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-TSSOP (BRURL7) | 28-TSSOP - same | 28-TSSOP - same | 28-TSSOP - same | 28-TSSOP - same | 28-TSSOP - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Max Sample Rate | 65 MSPS | 65 MSPS | 65 MSPS | 40 MSPS (-38%) | 20 MSPS (-69%) | 80 MSPS (+23%) |
| Supply Voltage | 3 V (2.7-3.6 V) | 3 V | 3 V | 3 V | 3 V | 3 V |
| Lead Finish (RoHS) | SnPb (legacy) | Pb-free / RoHS | SnPb (legacy) | SnPb (legacy) | SnPb (legacy) | Pb-free / RoHS |
| Packaging Form | Tape & Reel (7") | Tape & Reel (7") | Tube | Tape & Reel (7") | Tube | Tube |
| Pin Count | 28 | 28 | 28 | 28 | 28 | 28 |
주요 차별점
- Single 3 V analog supply, no negative rail needed (vs AD9235BRU-20)
- Integrated clock duty-cycle stabilizer (vs AD9235BRURL7-40)
- 500 MHz analog input bandwidth enables IF undersampling (vs AD9235BRU-65 (tube))
설계 노트
Estimated: at 65 MSPS and a single 3.0 V supply the AD9235BRURL7-65 draws ~100 mA (300 mW / 3 V). Apply a 10 uF + 0.1 uF local capacitor pair on each of AVDD, AVDD2, and DVDD - placed within 3 mm of their respective pins - to suppress switching-cell transient currents from coupling back through the supply. Use a ferrite bead between the analog and digital rails and join the grounds at a single-point star under the exposed pad or pin 11/14 region.
Estimated: route the differential analog inputs AIN+/AIN- as 50 ohm microstrip or stripline of matched length (delta <0.5 mm) and keep them away from digital output traces - digital switching noise couples easily into the SHA. The differential clock traces CLK+/CLK- should follow the same matched-length discipline. Reference the AVDD/AVDD2 returns directly to the analog ground plane, not the digital ground plane, and place the CML pin bypass cap directly at pin 12.
Avoid single-ended clock or analog-input drive - the AD9235's SHA is engineered for fully differential operation and the SNR/SFDR will degrade 10-20 dB with single-ended signals. Activate the clock-duty-cycle stabilizer (DCS) by tying pin 28 (DCS/PD) low via a 1 k resistor, or float it; tying it high puts the part into power-down. Decouple REFT and REFB at pins 8-9 with 10 uF + 0.1 uF ceramic across each; do not apply external load currents to these reference pins.
Estimated: total throughput SNR including jitter is SNR_total = -10*log10[(2*pi*f_in*t_j)^2 + (1/SNR_ADC)]; a 65 MSPS ADC and a 70 MHz IF require <2 ps RMS clock jitter to stay within 1 dB of the datasheet's 70 dBFS floor. Use a low-jitter TCXO or a clock-distribution IC such as AD9516 and confirm jitter-budget with a phase-noise analyzer before locking down the design.
규정 준수 정보
RL7 (non-Z) order code uses legacy lead-containing finish per Analog Devices naming convention; new designs should select the Z-suffix RoHS variant. AEC-Q100 not applicable for industrial/consumer ADC. REACH / halogen / conflict-mineral status not stated in retrieved datasheet preview.
