AD9629XCPZ-40 - 12-Bit, 40 MSPS ADC, 1.8V | Analog Devices
부품 번호: AD9629XCPZ-40 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.3 | $113.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.45 | $7,450.00 |
AD9629XCPZ-40 개요
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog signals into discrete digital codes at a specified sample rate. ADCs sit between the analog front end (sensors, amplifiers, filters) and the digital back end (DSP, FPGA, microcontroller), and their speed, resolution, and noise performance directly limit overall system fidelity. Within this hierarchy, the AD9629XCPZ-40 belongs to the category of pipeline ADCs (it is a successive-style 12-bit converter with an integrated input bandwidth and reference), a subfamily of data converters -> data acquisition -> mixed-signal ICs -> integrated circuits. ADCs are typically specified by sample rate (MSPS), resolution (bits), signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), input bandwidth, and power dissipation.
Key features include 12-bit resolution, 40 MSPS sample rate, single 1.8 V analog supply, low power consumption suitable for portable and battery-powered instrumentation, CMOS-compatible digital outputs, and a pin-compatible upgrade path to the 10-bit AD9609 and 14-bit AD9649 in the same LFCSP-32 package. The on-chip voltage reference reduces external BOM and PCB area, while the integrated sample-and-hold supports full Nyquist operation to over 40 MHz analog input bandwidth. The 1.8 V supply voltage enables direct interface to modern low-voltage FPGAs and ASICs without level shifters.
Typical applications include communications IF/RF digitisation, portable ultrasound imaging, handheld industrial instruments, low-cost digital oscilloscopes, multichannel data acquisition front ends, and software-defined radio (SDR) receiver IF stages. The AD9629's pin compatibility with the AD9609 (10-bit) and AD9649 (14-bit) makes it the natural choice for designers who want a single PCB layout that supports multiple resolution tiers or future upgrades without redesign.
When designing with this ADC, place the input network components as close to the analog input pins as possible to preserve SNR. Provide a low-impedance, low-noise analog supply with adequate decoupling to meet the published AC performance, and route the CMOS digital outputs away from the analog input traces to minimise digital-to-analog crosstalk. This page synthesises distributor pricing, drop-in pin-compatible alternatives from the same AD9609/AD9629/AD9649 family, and practical design notes not found in the manufacturer datasheet alone.
드롭인 대체품: AD9629XCPZ-40 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD9629XCPZ-40 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, Operating Temperature Range, Input Type, Number of Channels.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD9629XCPZ-65
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9629XCPZ-80
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9629XCPZ-20
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9609XCPZ-40
✅ 드롭인✓ 재고 있음
$5.4 / 개
데이터시트 보기 →AD9649XCPZ-40
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9649XCPZ-65
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9629XCPZ-40 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Sample Rate | 40 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V to 3.3 V |
| Input Type | Differential or single-ended |
| Reference | Internal (on-chip) |
| Data Interface | Parallel CMOS |
| 패키지 | 32-lead LFCSP (CP-32-3) |
| Package Dimensions | 5 mm x 5 mm |
| 동작 온도 범위 | -40C to +85C (industrial) |
| RoHS Compliance | Yes |
| Sample-and-Hold | Integrated on-chip |
| Pin Compatibility | Pin-compatible with AD9609 (10-bit) and AD9649 (14-bit) |
AD9629XCPZ-40 핀 구성
| 핀 1 | AIN+ — Differential analog input (positive) |
| 핀 2 | AIN- — Differential analog input (negative) |
| 핀 3 | VREF — Voltage reference decoupling |
| 핀 4 | AGND — Analog ground |
| 핀 5 | AVDD — 1.8 V analog supply |
| 핀 6 | CLK+ — Differential clock input (positive) |
| 핀 7 | CLK- — Differential clock input (negative) |
| 핀 8 | AVDD — 1.8 V analog supply |
| 핀 9 | AGND — Analog ground |
| 핀 10 | D11 — CMOS digital output bit 11 (MSB) |
| 핀 11 | D10 — CMOS digital output bit 10 |
| 핀 12 | D9 — CMOS digital output bit 9 |
| 핀 13 | D8 — CMOS digital output bit 8 |
| 핀 14 | D7 — CMOS digital output bit 7 |
| 핀 15 | D6 — CMOS digital output bit 6 |
| 핀 16 | D5 — CMOS digital output bit 5 |
| 핀 17 | DVDD — Digital supply (1.8 V to 3.3 V) |
| 핀 18 | D4 — CMOS digital output bit 4 |
| 핀 19 | D3 — CMOS digital output bit 3 |
| 핀 20 | D2 — CMOS digital output bit 2 |
| 핀 21 | D1 — CMOS digital output bit 1 |
| 핀 22 | D0 — CMOS digital output bit 0 (LSB) |
| 핀 23 | OTR — Out-of-range indicator |
| 핀 24 | DFS — Data format select |
| 핀 25 | CSB — Chip select (active low) |
| 핀 26 | SCLK — Serial clock for register configuration |
| 핀 27 | SDIO — Serial data input/output |
| 핀 28 | SDFS — Sync/frame alignment |
| 핀 29 | DVDD — Digital supply (1.8 V to 3.3 V) |
| 핀 30 | DGND — Digital ground |
| 핀 31 | PDWN — Power-down input |
| 핀 32 | AGND — Analog ground |
일반적인 애플리케이션
AD9629XCPZ-40 적합 용도: 6 애플리케이션s: Communications IF/RF Digitisation, Portable Ultrasound Imaging, Handheld Industrial Instrumentation, Low-Cost Digital Oscilloscope, Multichannel Data Acquisition Front End, Software-Defined Radio Receiver IF.
Communications IF/RF Digitisation
The AD9629XCPZ-40 is well-suited for digitising intermediate frequency (IF) signals in communications receivers up to approximately 20 MHz analog bandwidth at 40 MSPS. Its 12-bit resolution provides around 70 dB SNR, which preserves modulation fidelity for narrowband and wideband digital demodulation. Placed after the down-conversion mixer and anti-aliasing filter, the ADC feeds baseband samples directly into an FPGA or DSP running the demodulation algorithms. The 1.8 V supply reduces power in densely populated multi-channel receiver cards; pin-compatible 10-bit AD9609 and 14-bit AD9649 parts allow the same PCB to support different dynamic-range tiers.
추천
Portable Ultrasound Imaging
The AD9629XCPZ-40's 40 MSPS sample rate and 12-bit resolution match the bandwidth and dynamic range required for portable, hand-held ultrasound beamformer front ends digitising pre-beamformed RF or post-beamformed video signals. Low power consumption from the 1.8 V supply extends battery life in cart-based and wireless probe designs. Placed after the LNA, TGC, and anti-aliasing filter on each channel, the ADC drives the FPGA beamforming engine. Pin compatibility with the 14-bit AD9649 family preserves the layout for higher-channel-count, higher-end ultrasound carts.
추천
Handheld Industrial Instrumentation
The AD9629XCPZ-40 is an excellent fit for battery-powered handheld oscilloscopes, spectrum analysers, and field-installable vibration analysers because the 1.8 V supply reduces total power to a few hundred mW per channel at 40 MSPS. 12-bit resolution is sufficient for most general-purpose measurement tasks and 40 MSPS covers audio-bandwidth, vibration-bandwidth, and low-MHz RF-bandwidth signals. Placed after the input attenuator and front-end buffer, the ADC feeds an FPGA or microcontroller running FFT, envelope detection, or threshold logic.
추천
Low-Cost Digital Oscilloscope
For low-cost two-channel and four-channel digital oscilloscopes in the 20 MHz to 40 MHz bandwidth class, the AD9629XCPZ-40 provides the right balance of sample rate (40 MSPS), resolution (12 bits), and cost. The internal sample-and-hold eliminates an external track-and-hold IC, and the parallel CMOS outputs interface directly to low-cost FPGAs. Pin compatibility with the 65 MSPS AD9629XCPZ-65 and the 80 MSPS AD9629XCPZ-80 allows one PCB to serve 40 MHz, 65 MHz, or 80 MHz bandwidth SKUs.
추천
Multichannel Data Acquisition Front End
The AD9629XCPZ-40 is widely used as a single-channel digitiser in modular multichannel DAQ cards for vibration analysis, acoustic emission, and structural-health monitoring systems. Multiple AD9629XCPZ-40 parts clocked in parallel from a common low-jitter oscillator form a synchronised multi-MSample/s acquisition array. The 1.8 V supply and modest power dissipation simplify the thermal design of dense DAQ modules, while the 12-bit resolution captures the dominant spectral content of mechanical signals.
추천
Software-Defined Radio Receiver IF
The AD9629XCPZ-40 is well-suited to software-defined radio (SDR) receiver IF stages digitising 10 MHz to 20 MHz IF signals at 40 MSPS, feeding channelisation and demodulation logic in an FPGA. The 12-bit resolution gives approximately 70 dB SNR, which is adequate for many narrowband and broadband digital demodulation standards including DVB, DAB, FM, and amateur-radio modes. Pin compatibility with the 14-bit AD9649 family allows migration to higher dynamic-range SDRs on the same PCB layout.
추천
추천 제품 요약
엔지니어링 참조 데이터: AD9629XCPZ-40 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD9629XCPZ-65 | AD9629XCPZ-80 | AD9629XCPZ-20 | AD9609XCPZ-40 | AD9649XCPZ-40 | AD9649XCPZ-65 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 32-lead LFCSP (CP-32-3) | 32-lead LFCSP (CP-32-3) - same | 32-lead LFCSP (CP-32-3) - same | 32-lead LFCSP (CP-32-3) - same | 32-lead LFCSP (CP-32-3) - same | 32-lead LFCSP (CP-32-3) - same | 32-lead LFCSP (CP-32-3) - same |
| Resolution | 12 bits | 12 bits - same | 12 bits - same | 12 bits - same | 10 bits (-2 bits) | 14 bits (+2 bits) | 14 bits (+2 bits) |
| Sample Rate | 40 MSPS | 65 MSPS (+62.5%) | 80 MSPS (+100%) | 20 MSPS (-50%) | 40 MSPS - same | 40 MSPS - same | 65 MSPS (+62.5%) |
| Analog Supply Voltage | 1.8 V | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same |
| Number of Channels | 1 | 1 - same | 1 - same | 1 - same | 1 - same | 1 - same | 1 - same |
| Internal Reference | Yes | Yes - same | Yes - same | Yes - same | Yes - same | Yes - same | Yes - same |
| Pin Compatibility | Reference part (12-bit, 40 MSPS) | Same 32-pin LFCSP footprint | Same 32-pin LFCSP footprint | Same 32-pin LFCSP footprint | Same 32-pin LFCSP footprint | Same 32-pin LFCSP footprint | Same 32-pin LFCSP footprint |
주요 차별점
- Pin-compatible resolution upgrade path on the same PCB (vs AD9649XCPZ-40)
- Pin-compatible speed-grade scaling within the AD9629 family (vs AD9629XCPZ-65)
- Higher resolution than the pin-compatible 10-bit option (vs AD9609XCPZ-40)
설계 노트
Place the analog input network (anti-aliasing RC, common-mode choke, transformer/balun) within 5 mm of the AIN+/AIN- pins. Use a continuous analog ground plane on the top layer directly under the input traces, with vias stitching the top ground plane to the internal ground plane around the periphery of the ADC footprint. Per the Analog Devices AD9629 datasheet section 'PCB Layout Considerations', stray capacitance on the analog inputs above 2 pF degrades SNR at the higher input frequencies.
Estimated: at 40 MSPS, the AD9629XCPZ-40 typically dissipates approximately 110 mW from a clean 1.8 V AVDD. Decouple each AVDD pin with a 0.1 uF ceramic X7R placed within 1 mm of the pin plus a 10 uF tantalum or polymer bulk capacitor on the supply plane. Use a ferrite bead or small LRC pi-filter between the analog and digital 1.8 V rails to prevent digital switching noise coupling into the sensitive analog supply; route the analog 1.8 V plane separately and join only at the ferrite bead.
Use a low-jitter (sub-1 ps RMS) differential clock source such as the AD9523 or ADCLK946 to drive the CLK+/CLK- inputs; clock jitter directly degrades SNR at high analog input frequencies according to SNR = 20*log10(1/(2*pi*Fin*Tjitter)). Keep the digital CMOS output traces short and route them on a separate layer or opposite side of the ground plane away from the analog input traces, terminated with a small series resistor (22-33 ohm) near the ADC to dampen the high-frequency content of the output edges.
Do not float the exposed thermal pad on the bottom of the LFCSP-32 package - it must be soldered to a low-impedance analog ground pad with multiple thermal vias to the ground plane; failing to do so raises the die temperature and can cause SNR drift or latch-up. Avoid routing the CMOS output bus directly under the ADC body; the on-chip bond wires can couple switching noise back into the analog inputs and degrade SFDR by 5-10 dB at full-scale input.
규정 준수 정보
RoHS compliant per Analog Devices product page; not AEC-Q100 qualified - this is a commercial/industrial part. Lead-free reflow profile per JEDEC J-STD-020 applies.
