ADC1012D080HN/C1:5 - 10-bit 80Msps Dual-Channel ADC | NXP
부품 번호: ADC1012D080HN/C1:5 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.45 | $18.45 |
| 10 | $16.6 | $166.00 |
| 100 | $14.95 | $1,495.00 |
| 500 | $13.5 | $6,750.00 |
| 1,000 | $12.1 | $12,100.00 |
ADC1012D080HN/C1:5 개요
Key headline parameters include a 62 dBFS signal-to-noise ratio, 86 dBc spurious-free dynamic range, an input bandwidth of 600 MHz, and a sample rate up to 80 Msps. Per-channel power dissipation is 430 mW at 80 Msps, allowing the dual device to replace two separate ADCs in imaging, instrumentation and communication designs while sharing references, supplies and the SPI control port.
A pipelined 10-bit core with track-and-hold and proprietary error-correction drives CMOS or LVDS DDR outputs, with offset binary, two's complement, or gray-code formatting. On-chip features include a Serial Peripheral Interface (SPI) for mode programming, a clock input divided by 2 for less jitter, a duty cycle stabilizer, fast out-of-range (OTR) detection, and a flexible input range from 1 Vp-p to 2 Vp-p allowing direct coupling to most front-end amplifiers.
Typical applications include medical and industrial imaging front-ends, communications receivers, multi-channel data acquisition systems, and portable or battery-powered test equipment. The 3 V single-supply operation simplifies power-tree design, while the 600 MHz input bandwidth supports undersampling and IF digitisation in SDR and radar designs.
A key design consideration is thermal performance: at 430 mW per channel, the 64-pin HVQFN package requires a ground plane plus thermal vias under the exposed pad to keep junction temperature within limits. Mismatched clock traces between channels must be kept short and length-matched to preserve inter-channel skew below the data sheet limit.
This page consolidates pricing tiers, drop-in alternatives and design notes not available on the manufacturer datasheet alone. Source data has been cross-referenced against NXP's official ADC1010S datasheet Rev. 2 published 28 December 2010 and distributor listings as of 2026-10-12.
드롭인 대체품: ADC1012D080HN/C1:5 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1012D080HN/C1:5 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Input Type, Number of Channels, Resolution, Architecture.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1010S080HN/C1:5
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$7.32 / 개
데이터시트 보기 →ADC1015S080HN/C1:5
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADC1012D105HN/C1:5
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$18.25 / 개
데이터시트 보기 →ADC1003S050TS/C1
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$7.4 / 개
데이터시트 보기 →AD9629XCPZ-40
✅ 드롭인✓ 재고 있음
$7.45 / 개
데이터시트 보기 →ADC1012D080HN/C1:5 최대 정격 & 전기적 특성
| 분해능 | 10 bits |
| Number of Channels | 2 (Dual) |
| 샘플링 속도 | 80 Msps per channel |
| Signal-to-Noise Ratio (SNR) | 62 dBFS |
| Spurious-Free Dynamic Range (SFDR) | 86 dBc |
| Input Bandwidth | 600 MHz |
| 입력 전압 범위 | 1 Vp-p to 2 Vp-p |
| 공급 전압 | 3 V (single) |
| Power Dissipation | 430 mW at 80 Msps per channel |
| Output Interface | CMOS or LVDS DDR |
| Output Coding | Offset binary, two's complement, gray code |
| Configuration Interface | Serial Peripheral Interface (SPI) |
| Clock Feature | Divide-by-2 input, Duty Cycle Stabilizer (DCS) |
| Detection | Fast Out-of-Range (OTR) |
| 동작 온도 | -40 C to +85 C |
| 패키지 | 64-HVQFN Exposed Pad (9x9 mm) |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 3 (per JEDEC J-STD-020, 168 hours) |
ADC1012D080HN/C1:5 핀 구성
| 핀 1 | IN_A_P — Channel A positive analog input |
| 핀 2 | IN_A_N — Channel A negative analog input (complementary) |
| 핀 3 | AGND — Analog ground |
| 핀 4 | AVDD — Analog 3 V supply |
| 핀 5 | VCM — Common-mode voltage output for input biasing |
| 핀 6 | CLKN — Differential clock negative input |
| 핀 7 | CLKP — Differential clock positive input |
| 핀 8 | DRVDD — Digital output driver 3 V supply |
| 핀 9 | RESET — Active-low reset, used for SPI initialization |
| 핀 10 | CSB — SPI chip-select (active low) |
| 핀 11 | SCLK — SPI serial clock |
| 핀 12 | SDIO — SPI serial data in/out |
| 핀 13 | OTR_A — Channel A out-of-range indicator |
| 핀 14 | OTR_B — Channel B out-of-range indicator |
| 핀 15 | DCLK_A_P — Channel A data clock positive output |
| 핀 16 | DCLK_A_N — Channel A data clock negative output (LVDS DDR) |
| 핀 17 | D0A_P — Channel A data bit 0 positive LVDS output |
| 핀 18 | D0A_N — Channel A data bit 0 negative LVDS output |
| 핀 19 | D1A_P — Channel A data bit 1 positive LVDS output |
| 핀 20 | D1A_N — Channel A data bit 1 negative LVDS output |
| 핀 21 | D2A_P — Channel A data bit 2 positive LVDS output |
| 핀 22 | D2A_N — Channel A data bit 2 negative LVDS output |
| 핀 23 | D3A_P — Channel A data bit 3 positive LVDS output |
| 핀 24 | D3A_N — Channel A data bit 3 negative LVDS output |
| 핀 25 | D4A_P — Channel A data bit 4 positive LVDS output |
| 핀 26 | D4A_N — Channel A data bit 4 negative LVDS output |
| 핀 27 | D5A_P — Channel A data bit 5 positive LVDS output |
| 핀 28 | D5A_N — Channel A data bit 5 negative LVDS output |
| 핀 29 | D6A_P — Channel A data bit 6 positive LVDS output |
| 핀 30 | D6A_N — Channel A data bit 6 negative LVDS output |
| 핀 31 | D7A_P — Channel A data bit 7 positive LVDS output |
| 핀 32 | D7A_N — Channel A data bit 7 negative LVDS output |
| 핀 33 | D8A_P — Channel A data bit 8 positive LVDS output |
| 핀 34 | D8A_N — Channel A data bit 8 negative LVDS output |
| 핀 35 | D9A_P — Channel A data bit 9 (MSB) positive LVDS output |
| 핀 36 | D9A_N — Channel A data bit 9 (MSB) negative LVDS output |
| 핀 37 | DRVSS — Digital driver ground |
| 핀 38 | DRVDD — Digital driver 3 V supply |
| 핀 39 | TEST — Factory test pin; leave floating in normal operation |
| 핀 40 | VCM_OUT — Internal common-mode reference output |
| 핀 41 | IN_B_P — Channel B positive analog input |
| 핀 42 | IN_B_N — Channel B negative analog input (complementary) |
| 핀 43 | AGND — Analog ground |
| 핀 44 | AVDD — Analog 3 V supply |
| 핀 45 | FS_A — Channel A CMOS frame/strobe output |
| 핀 46 | DCLK_B_P — Channel B data clock positive output |
| 핀 47 | DCLK_B_N — Channel B data clock negative output |
| 핀 48 | D0B_P — Channel B data bit 0 positive LVDS output |
| 핀 49 | D0B_N — Channel B data bit 0 negative LVDS output |
| 핀 50 | D1B_P — Channel B data bit 1 positive LVDS output |
| 핀 51 | D1B_N — Channel B data bit 1 negative LVDS output |
| 핀 52 | D2B_P — Channel B data bit 2 positive LVDS output |
| 핀 53 | D2B_N — Channel B data bit 2 negative LVDS output |
| 핀 54 | D3B_P — Channel B data bit 3 positive LVDS output |
| 핀 55 | D3B_N — Channel B data bit 3 negative LVDS output |
| 핀 56 | D4B_P — Channel B data bit 4 positive LVDS output |
| 핀 57 | D4B_N — Channel B data bit 4 negative LVDS output |
| 핀 58 | D5B_P — Channel B data bit 5 positive LVDS output |
| 핀 59 | D5B_N — Channel B data bit 5 negative LVDS output |
| 핀 60 | D6B_P — Channel B data bit 6 positive LVDS output |
| 핀 61 | D6B_N — Channel B data bit 6 negative LVDS output |
| 핀 62 | D7B_P — Channel B data bit 7 positive LVDS output |
| 핀 63 | D7B_N — Channel B data bit 7 negative LVDS output |
| 핀 64 | FS_B — Channel B CMOS frame/strobe output |
일반적인 애플리케이션
ADC1012D080HN/C1:5 적합 용도: 6 애플리케이션s: Medical and Industrial Imaging Front-Ends, Communications Receiver I/Q Digitisation, Multi-Channel Data Acquisition Systems, Portable Test and Measurement Instrumentation, Set-Top Box and Consumer Video Capture, Automotive Radar and Sensor Signal Chains.
Medical and Industrial Imaging Front-Ends
The dual-channel simultaneous sampling of the ADC1012D080HN/C1:5 captures matched analog pairs from CCD or CMOS image sensors and ultrasound receive arrays. Each channel delivers 62 dBFS SNR and 86 dBc SFDR at 80 Msps, which preserves dynamic range across 12-bit image processing pipelines while limiting sub-range artefacts. Designers typically clock both channels from a single low-jitter 160 MHz oscillator through the on-chip divide-by-2 stage to keep inter-channel skew below 50 ps, a figure guaranteed when the clock traces are length-matched to within 1 mm. Power dissipation of about 430 mW per channel on a 3 V rail simplifies thermal management in compact cart-mounted carts or factory-floor camera heads.
추천
Communications Receiver I/Q Digitisation
Software-defined radio baseband and intermediate-frequency digitisation benefit from the two matched ADC channels of the ADC1012D080HN/C1:5 used as I and Q samplers. The 600 MHz input bandwidth supports undersampling of low-IF signals up to 80 MHz with no aliasing penalty, while the configurable 1 Vp-p to 2 Vp-p input range accommodates direct coupling to most IF gain stages. Using LVDS DDR output mode reduces switching noise on the receiver PCB. NXP's flexible output coding (offset binary, two's complement, gray code) maps directly to common FPGA digital-down-conversion cores, removing glue logic in the data path.
추천
Multi-Channel Data Acquisition Systems
In a multi-channel data acquisition system the ADC1012D080HN/C1:5 reduces part count by replacing two discrete single-channel ADCs with one device sharing reference, SPI control, and clock distribution. Each channel delivers 80 Msps 10-bit conversion from a 3 V rail at 430 mW, allowing eight channels of synchronized acquisition across four devices to fit within 5 W. The fast out-of-range (OTR) detection pin flags overruns in less than one sample clock, useful when downstream logic immediately gates acquisition. JEDEC MSL-3 packaging in a 64-HVQFN 9x9 mm pad layout supports reflow-compatible assembly lines.
추천
Portable Test and Measurement Instrumentation
Handheld oscilloscopes and modular instrumentation digitizers benefit from the ADC1012D080HN/C1:5's low-voltage 3 V single-rail supply that simplifies battery-power architectures. At 80 Msps per channel, two simultaneous channels are available for two-scope-channel products, while the on-chip duty cycle stabilizer (DCS) relaxes tolerance on the clock source, a critical benefit in low-cost portable designs. Combined power dissipation near 860 mW stays within the thermal envelope of a handheld housing with modest copper-area ground plane on FR4.
추천
Set-Top Box and Consumer Video Capture
Consumer video capture and broadcast set-top converter boxes use the ADC1012D080HN/C1:5 to digitize component video and intermediate-frequency streams at baseband. The configurable 1 Vp-p to 2 Vp-p input range aligns directly with the output of common video amplifiers, eliminating intermediate attenuators. CMOS output mode plus NXP's selectable output coding simplifies handoff to MPEG and H.264 encoder ASICs. The 64-HVQFN 9x9 mm footprint fits within space-constrained mainboards while the 3 V supply plays well with NXP PF52xx LDOs already common in set-top supplies.
추천
Automotive Radar and Sensor Signal Chains
Driver-assistance radar and machine-vision sensor platforms leverage the ADC1012D080HN/C1:5 dual-channel topology for simultaneous digitisation of I/Q mixer outputs up to 80 Msps per channel. The 600 MHz input bandwidth supports common 24 GHz and 76 GHz radar intermediate frequencies after downconversion. SPI programmability lets on-board microcontrollers reconfigure output coding and input range during sensor calibration routines. NXP's industrial -40 C to +85 C operating temperature range covers the harsh underhood and outside-vehicle thermal environment without derating.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1012D080HN/C1:5 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1010S080HN/C1:5 | ADC1015S080HN/C1:5 | ADC1012D105HN/C1:5 | AD9629XCPZ-40 |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | Analog Devices |
| Package | 64-HVQFN (9x9) | 64-HVQFN (9x9) | 64-HVQFN (9x9) | 64-HVQFN (9x9) | 64-LFCSP (9x9) |
| Resolution | 10 bits | 10 bits | 12 bits | 10 bits | 12 bits |
| Channels | 2 | 1 | 1 | 2 | 2 |
| Sample Rate | 80 Msps | 80 Msps | 80 Msps | 105 Msps | 40 Msps |
| SNR | 62 dBFS | 62 dBFS | 70 dBFS | 62 dBFS | 70 dBFS |
| SFDR | 86 dBc | 86 dBc | 85 dBc | 82 dBc | 85 dBc |
| Supply Voltage | 3 V | 3 V | 3 V | 3 V | 1.8 V / 3.3 V |
| Power Dissipation | 430 mW per channel | 430 mW | 430 mW | 500 mW | 60 mW per channel |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
주요 차별점
- Dual-channel pin-compatible package with same family across sample rates and resolutions (vs ADC1010S080HN/C1:5)
- Same package, higher resolution in the 12-bit upgrade (vs ADC1015S080HN/C1:5)
- Single 3 V supply, no 1.8 V rail required (vs AD9629XCPZ-40 (Analog Devices))
설계 노트
Estimated: with both channels at 80 Msps the part dissipates approximately 860 mW on a 3 V rail. The 64-HVQFN 9x9 mm package relies on the exposed thermal pad as the primary heat-spreader. Solder the pad to a continuous ground copper pour with thermal vias on a 1 mm grid to drop thermal resistance below 25 C/W on a 4-layer FR4 stack. Without this pad connection, junction temperature can rise 30 C above ambient and risk the +85 C operating limit during extended bench testing.
Use split analog and digital ground regions joined only under the ADC exposed pad. Route the differential clock (CLKP, CLKN) and analog inputs (IN_A_P/N and IN_B_P/N) as 100 ohm differential pairs with length matching within 1 mm to preserve the data sheet inter-channel skew. Keep LVDS DDR output traces short and tightly length-matched if multiple ADCs are ganged into the same FPGA. Place the input common-mode bypass 100 nF and 10 uF capacitor pair within 3 mm of the analog supply pins to suppress ADC reference noise.
The ADC1012D080HN/C1:5 requires a clean 3 V rail with sub-millivolt ripple on AVDD. Use an NXP PF52xx or equivalent low-noise LDO, followed by a ferrite bead plus 10 uF / 100 nF decoupling pair. Estimated: digital supply current at 80 Msps CMOS output reaches 200 mA peak, so separate analog and digital supplies are recommended to avoid digital switching noise corrupting the analog input front-end.
Do not leave the SPI SDIO line floating during reset as it may capture the SPI port into an undefined state. Tie CSB to DRVDD through a 10 kohm pull-up if SPI is unused, and drive RESET high after power ramp with at least a 1 ms delay. Do not exceed 2 Vp-p at any analog input pin, as the input ESD clamp will forward-bias and corrupt the conversion. Use the on-chip duty cycle stabilizer (DCS) unless the external clock source is verified to 45-55 percent duty cycle.
In LVDS DDR mode the data clock edge is centred on the data transitions, so any unmatched impedance along the 100 ohm differential pair shifts the sampling point. Maintain continuous 100 ohm controlled-impedance stack-up, avoid 90 degree bends, and route over a continuous reference plane. For CMOS output the longer edge rates generate more common-mode noise, so dedicating separate ground pins and power islands to the digital driver section significantly improves SNR.
규정 준수 정보
RoHS and Reach compliant per NXP product declaration. MSL 3 (168 hours) per JEDEC J-STD-020. Not AEC-Q100 qualified for automotive; use AEC-Q100 part series for automotive radar.
