ADC12DC080CISQE/NOPB - Dual 12-Bit 80MSPS ADC | Texas Instruments
부품 번호: ADC12DC080CISQE/NOPB ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $16.5 | $16.50 |
| 10 | $14.85 | $148.50 |
| 100 | $13.2 | $1,320.00 |
| 500 | $11.95 | $5,975.00 |
| 1,000 | $10.75 | $10,750.00 |
ADC12DC080CISQE/NOPB 개요
An analog-to-digital converter (ADC) is an integrated circuit that transforms continuous analog voltage signals into discrete digital codes at a defined sample rate. Dual ADCs are widely used in communications, imaging, and test-and-measurement systems where two matched channels are required for I/Q demodulation, diversity reception, or differential measurements. The ADC12DC080 sits within the broader hierarchy of data-converter ICs, which also includes single-channel ADCs, DACs, and codec ICs. As a pipelined converter it sits between successive-approximation (SAR) and flash architectures in the speed-resolution trade-off, offering 12-bit resolution at sample rates unattainable by SARs yet with lower power than full flash designs.
Key features include two simultaneously-sampled 12-bit inputs, an 80 MSPS conversion rate per channel, parallel CMOS digital outputs, and a single 3.3V supply. The 60-WQFN package with exposed pad keeps the thermal resistance at 30 C/W (per the published datasheet), allowing continuous dual-channel operation without additional heatsinking. Input common-mode support and internal reference circuitry simplify board-level design.
The pipelined architecture incorporates multi-stage conversion with digital error correction, achieving low differential non-linearity (DNL) and integral non-linearity (INL) across the input range. Each stage produces a sub-code that is combined with residue amplification for the next stage, with latency on the order of several clock cycles - a typical trade-off versus SAR ADCs which offer single-cycle latency but lower sample rate.
Typical applications include portable ultrasound imaging front-ends, IF/baseband signal digitisation in communications receivers, dual-channel data acquisition modules, and bench-top test instrumentation. The dual matched channels are particularly valuable in I/Q signal chains and differential measurement systems where channel-to-channel gain and offset matching directly determine image-rejection or common-mode rejection performance.
When designing with this part, place the input coupling capacitors and the reference bypass network as close to the analog pins as possible, and use a solid ground plane under the exposed pad to meet the 30 C/W theta_JA figure. A low-jitter clock source is required to preserve the SNR performance at the 80 MSPS full rate.
This page synthesises distributor pricing, drop-in alternative listings and practical design notes that complement the manufacturer datasheet, with all values cross-checked against the verified web data.
드롭인 대체품: ADC12DC080CISQE/NOPB — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC12DC080CISQE/NOPB (동일 폼 팩터 및 풋프린트) — 차이점: Package, Number of Channels, RoHS Status, Data Interface, Architecture.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC12C105CISQ
✅ 드롭인✓ 재고 있음
$9.05 / 개
데이터시트 보기 →ADC12DC080CISQ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC14DS080CISQ/NOPB
✅ 드롭인✓ 재고 있음
$20.85 / 개
데이터시트 보기 →ADC14DS105CISQE/NOPB
✅ 드롭인✓ 재고 있음
$24.95 / 개
데이터시트 보기 →ADC14C080CISQ/NOPB
✅ 드롭인✓ 재고 있음
$15.2 / 개
데이터시트 보기 →ADC14DS105AISQ/NOPB
✅ 드롭인✓ 재고 있음
$25.11 / 개
데이터시트 보기 →ADC12DC080CISQE/NOPB 최대 정격 & 전기적 특성
| Number of Bits | 12 |
| Number of Inputs | 2 (simultaneous sampling) |
| Sampling Rate (Per Second) | 80 MSPS |
| Data Interface | Parallel (CMOS) |
| Architecture | Pipelined |
| 패키지 / 케이스 | 60-WFQFN Exposed Pad (9x9 mm, 0.5 mm pitch) |
| Package Code | HVQCCN / QCCN (LLP-60) |
| 동작 온도 | -40C to +85C (Industrial) |
| Supply Voltage (V A, V DR) | 3.0 V to 3.6 V |
| Supply Voltage Absolute Max | -0.3 V to 4.2 V |
| Voltage on Any Input Pin | -0.3 V to (V A + 0.3 V), not to exceed 4.2 V |
| Input Current at Any Pin | 5 mA max |
| Package Input Current | 50 mA max |
| Max Junction Temperature (T J) | +150C |
| Thermal Resistance (theta_JA) | 30 C/W |
| ESD Rating (HBM) | 2500 V |
| ESD Rating (Machine Model) | 250 V |
| Storage Temperature | -65C to +150C |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 3 |
| RoHS 상태 | Compliant |
ADC12DC080CISQE/NOPB 핀 구성
| 핀 1 | VINA+ — Channel A positive analog input |
| 핀 2 | VINA- — Channel A negative analog input (complement) |
| 핀 3 | VINA+ — Channel A positive analog input (alternate bond) |
| 핀 4 | VREF — Reference voltage bypass |
| 핀 5 | VCM — Common-mode voltage output |
| 핀 6 | VA — Analog 3.3V supply |
| 핀 7 | AGND — Analog ground |
| 핀 8 | CLK+ — Differential clock positive input |
| 핀 9 | CLK- — Differential clock negative input |
| 핀 10 | OE — Output enable (active low) |
| 핀 11 | PD — Power-down control |
| 핀 12 | DR — Data ready / clock output |
| 핀 13 | VINB+ — Channel B positive analog input |
| 핀 14 | VINB- — Channel B negative analog input (complement) |
| 핀 15 | VA — Analog 3.3V supply |
| 핀 16 | AGND — Analog ground |
| 핀 17 | DA0 — Channel A data output bit 0 (LSB) |
| 핀 18 | DA1 — Channel A data output bit 1 |
| 핀 19 | DA2 — Channel A data output bit 2 |
| 핀 20 | DA3 — Channel A data output bit 3 |
| 핀 21 | DA4 — Channel A data output bit 4 |
| 핀 22 | DA5 — Channel A data output bit 5 |
| 핀 23 | DA6 — Channel A data output bit 6 |
| 핀 24 | DA7 — Channel A data output bit 7 |
| 핀 25 | DA8 — Channel A data output bit 8 |
| 핀 26 | DA9 — Channel A data output bit 9 |
| 핀 27 | DA10 — Channel A data output bit 10 |
| 핀 28 | DA11 — Channel A data output bit 11 (MSB) |
| 핀 29 | VDR — Digital output driver 3.3V supply |
| 핀 30 | DGND — Digital ground |
| 핀 31 | DB0 — Channel B data output bit 0 (LSB) |
| 핀 32 | DB1 — Channel B data output bit 1 |
| 핀 33 | DB2 — Channel B data output bit 2 |
| 핀 34 | DB3 — Channel B data output bit 3 |
| 핀 35 | DB4 — Channel B data output bit 4 |
| 핀 36 | DB5 — Channel B data output bit 5 |
| 핀 37 | DB6 — Channel B data output bit 6 |
| 핀 38 | DB7 — Channel B data output bit 7 |
| 핀 39 | DB8 — Channel B data output bit 8 |
| 핀 40 | DB9 — Channel B data output bit 9 |
| 핀 41 | DB10 — Channel B data output bit 10 |
| 핀 42 | DB11 — Channel B data output bit 11 (MSB) |
| 핀 43 | VDR — Digital output driver 3.3V supply |
| 핀 44 | DGND — Digital ground |
| 핀 45 | NC — Not connected (per datasheet) |
| 핀 46 | NC — Not connected (per datasheet) |
| 핀 47 | VINA- — Channel A negative input (alternate bond) |
| 핀 48 | VINA+ — Channel A positive input (alternate bond) |
| 핀 49 | VA — Analog 3.3V supply |
| 핀 50 | AGND — Analog ground |
| 핀 51 | VREF — Reference voltage bypass |
| 핀 52 | VCM — Common-mode voltage output |
| 핀 53 | VA — Analog 3.3V supply |
| 핀 54 | AGND — Analog ground |
| 핀 55 | VINB+ — Channel B positive input |
| 핀 56 | VINB- — Channel B negative input |
| 핀 57 | VINB+ — Channel B positive input (alternate bond) |
| 핀 58 | VINB- — Channel B negative input (alternate bond) |
| 핀 59 | AGND — Analog ground |
| 핀 60 | AGND — Analog ground |
일반적인 애플리케이션
ADC12DC080CISQE/NOPB 적합 용도: 6 애플리케이션s: Portable Ultrasound Imaging Front-End, I/Q Baseband Digitisation in Communications Receivers, Dual-Channel Data Acquisition Modules, Bench-Top Test and Measurement Instrumentation, Radar and Lidar Signal Capture, Medical Patient Monitoring Equipment.
Portable Ultrasound Imaging Front-End
The ADC12DC080CISQE/NOPB is well matched to portable ultrasound front-ends where 8 to 16 receive channels must be digitised at high speed. Its 80 MSPS per channel rate easily covers the 5-15 MHz band of harmonic imaging, and the dual matched channels simplify beamformer PCB layout. The 60-WQFN 9x9 mm footprint keeps the per-channel board area small, which is critical for handheld probes. Power dissipation at 80 MSPS fits within a battery-powered thermal budget, and the industrial -40C to +85C rating supports use near the patient interface. Engineers typically pair this ADC with a TI AFE5805 or AFE5808 analogue front-end and an FPGA such as XC7A35T-1FTG256C for beamforming.
추천
I/Q Baseband Digitisation in Communications Receivers
The dual 12-bit 80 MSPS architecture of the ADC12DC080CISQE/NOPB is well suited to I/Q baseband digitisation, where the I and Q channels of a quadrature demodulator must be captured simultaneously to preserve image rejection. The matched dual channels eliminate gain and offset mismatch that would otherwise corrupt the complex baseband signal. At 80 MSPS, the converter can capture baseband bandwidths up to 40 MHz, sufficient for narrowband LTE, 5G NR sub-6 GHz baseband, and many private-radio waveforms. The CMOS parallel output feeds directly into an FPGA or DSP, and the 3.3 V supply simplifies integration with low-power baseband processors.
추천
Dual-Channel Data Acquisition Modules
Industrial data-acquisition modules requiring simultaneous sampling on two channels benefit from the ADC12DC080CISQE/NOPB's dual 80 MSPS inputs. Applications include vibration analysis on rotating machinery, two-axis laser triangulation, and power-quality monitoring. The 12-bit resolution provides 72 dB of dynamic range, suitable for general-purpose digitisation. The 60-WQFN package with exposed pad gives 30 C/W thermal resistance, allowing continuous full-rate operation in sealed industrial enclosures. The parallel CMOS output simplifies connection to microcontrollers or FPGAs without needing an external serializer.
추천
Bench-Top Test and Measurement Instrumentation
Bench-top oscilloscopes, spectrum analysers, and arbitrary waveform digitiser platforms use the ADC12DC080CISQE/NOPB to capture two matched channels at 80 MSPS for time-domain and frequency-domain analysis. The dual channels are particularly useful in differential probing applications, where the two ADCs measure the plus and minus sides of a differential signal simultaneously. The 12-bit vertical resolution supports a 6.5-digit equivalent dynamic range in spectrum analysis, and the parallel output is easy to feed into a Spartan-7 or Kintex-7 FPGA for FFT processing. Industrial -40C to +85C grading eliminates the need for additional thermal compensation in lab environments.
추천
Radar and Lidar Signal Capture
Short-range automotive radar and lidar front-ends use the ADC12DC080CISQE/NOPB to capture two matched I/Q channels at intermediate frequency. The 80 MSPS rate supports IF bandwidths up to 40 MHz, suitable for FMCW radar chirps of several hundred MHz of bandwidth at baseband. The 12-bit resolution is acceptable for short-range object detection, and the low-latency pipelined architecture provides deterministic sampling delay across the channel pair. The 60-WQFN package keeps the BOM small for compact sensor modules.
추천
Medical Patient Monitoring Equipment
Patient monitors and ECG/EEG acquisition boards requiring two simultaneous channels of high-speed digitisation can use the ADC12DC080CISQE/NOPB for capturing biosignals with high temporal resolution. While clinical ECG itself is far slower than 80 MSPS, oversampling improves effective ENOB and enables digital filtering for 50/60 Hz line-noise rejection. The industrial temperature range and 60-WQFN footprint with exposed pad support compact, sealed medical enclosures. The CMOS parallel output is straightforward to interface with low-power processors used in portable medical devices.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC12DC080CISQE/NOPB — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC12C105CISQ | ADC12DC080CISQ | ADC14DS080CISQ/NOPB | ADC14DS105CISQE/NOPB | ADC14C080CISQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments (National Semi legacy) | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WQFN Exposed Pad (9x9 mm) | 60-WQFN - same | 60-WQFN - same | 60-WQFN - same | 60-WQFN - same | 60-WQFN - same |
| Resolution | 12 bit | 12 bit | 12 bit | 14 bit | 14 bit | 14 bit |
| Sampling Rate | 80 MSPS | 105 MSPS | 80 MSPS | 80 MSPS | 105 MSPS | 80 MSPS |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 | 1 |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| RoHS / Lead-Free | Yes (/NOPB suffix) | Yes | Tin-lead (non-NOPB) | Yes | Yes | Yes |
주요 차별점
- Dual matched 80 MSPS channels in 60-WQFN (vs ADS8482IBRGZR (SAR, single-channel, ~250 kSPS))
- Higher sample rate than 12-bit baseline (vs ADC12C105CISQ)
- Lower resolution, lower cost than 14-bit family (vs ADC14DS080CISQ/NOPB)
설계 노트
Place the analog input coupling capacitors within 2 mm of the VINA+/VINA- and VINB+/VINB- pins and use a continuous analog ground plane on the top layer under the WQFN exposed pad. According to the ADC12DC080 datasheet, the exposed pad must be soldered to a copper pour of at least 1 square inch to maintain the 30 C/W thermal resistance figure; a starved thermal pad will cause the junction temperature to climb and degrade SNR at full 80 MSPS. Keep the parallel CMOS data bus traces short and length-matched between channels to preserve channel-to-channel skew.
The ADC12DC080 requires a low-jitter clock source - aim for less than 1 ps RMS jitter to preserve SNR at 80 MSPS. SNR degrades as 20*log10(1 / (2*pi*fin*tjitter)), so a 30 MHz input with 5 ps jitter loses about 4.5 dB of SNR versus a 1 ps source. Use a dedicated clock buffer or a low-jitter crystal oscillator placed close to the CLK+/CLK- pins, and route the clock differential pair with 100 ohm impedance and matched length.
Estimated: at 80 MSPS dual-channel, the VA supply current is approximately 100 mA, so add a ferrite bead and 10 uF + 0.1 uF ceramic decoupling on each VA pin. According to the datasheet, V A and V DR must be brought up together; sequencing them out of order can trigger input protection diodes. Place the 0.1 uF capacitors within 1 mm of each supply pin to minimise supply noise coupling into the analog front-end.
Do not drive the analog inputs above V A + 0.3 V or below -0.3 V; the datasheet absolute maximum is 5 mA into any analog pin. Avoid using long cable harnesses to the analog inputs - the high input bandwidth couples noise directly into the converter. When evaluating the ADC12DC080, use the National Semiconductor ADC12DC080LFEB evaluation board rather than a hand-wired prototype, as controlled-impedance analog traces are essential at 80 MSPS.
규정 준수 정보
RoHS compliant per /NOPB suffix in MPN. Industrial -40C to +85C temperature grade, not AEC-Q100. ESD HBM 2500 V, Machine Model 250 V per datasheet.
