ADC12DC080CISQE/NOPB - Dual 12-Bit 80MSPS ADC | Texas Instruments
MPN: ADC12DC080CISQE/NOPB ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.5 | $16.50 |
| 10 | $14.85 | $148.50 |
| 100 | $13.2 | $1,320.00 |
| 500 | $11.95 | $5,975.00 |
| 1,000 | $10.75 | $10,750.00 |
ADC12DC080CISQE/NOPB Overview
An analog-to-digital converter (ADC) is an integrated circuit that transforms continuous analog voltage signals into discrete digital codes at a defined sample rate. Dual ADCs are widely used in communications, imaging, and test-and-measurement systems where two matched channels are required for I/Q demodulation, diversity reception, or differential measurements. The ADC12DC080 sits within the broader hierarchy of data-converter ICs, which also includes single-channel ADCs, DACs, and codec ICs. As a pipelined converter it sits between successive-approximation (SAR) and flash architectures in the speed-resolution trade-off, offering 12-bit resolution at sample rates unattainable by SARs yet with lower power than full flash designs.
Key features include two simultaneously-sampled 12-bit inputs, an 80 MSPS conversion rate per channel, parallel CMOS digital outputs, and a single 3.3V supply. The 60-WQFN package with exposed pad keeps the thermal resistance at 30 C/W (per the published datasheet), allowing continuous dual-channel operation without additional heatsinking. Input common-mode support and internal reference circuitry simplify board-level design.
The pipelined architecture incorporates multi-stage conversion with digital error correction, achieving low differential non-linearity (DNL) and integral non-linearity (INL) across the input range. Each stage produces a sub-code that is combined with residue amplification for the next stage, with latency on the order of several clock cycles - a typical trade-off versus SAR ADCs which offer single-cycle latency but lower sample rate.
Typical applications include portable ultrasound imaging front-ends, IF/baseband signal digitisation in communications receivers, dual-channel data acquisition modules, and bench-top test instrumentation. The dual matched channels are particularly valuable in I/Q signal chains and differential measurement systems where channel-to-channel gain and offset matching directly determine image-rejection or common-mode rejection performance.
When designing with this part, place the input coupling capacitors and the reference bypass network as close to the analog pins as possible, and use a solid ground plane under the exposed pad to meet the 30 C/W theta_JA figure. A low-jitter clock source is required to preserve the SNR performance at the 80 MSPS full rate.
This page synthesises distributor pricing, drop-in alternative listings and practical design notes that complement the manufacturer datasheet, with all values cross-checked against the verified web data.
Drop-in alternatives for ADC12DC080CISQE/NOPB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC12DC080CISQE/NOPB (same form factor and footprint) — differing in Package, Number of Channels, RoHS Status, Data Interface, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC12C105CISQ
✅ Drop-In✓ In Stock
$9.05 / Unit
View Datasheet →ADC12DC080CISQ
✅ Drop-In📋 Reference alternative (not in catalog)
ADC14DS080CISQ/NOPB
✅ Drop-In✓ In Stock
$20.85 / Unit
View Datasheet →ADC14DS105CISQE/NOPB
✅ Drop-In✓ In Stock
$24.95 / Unit
View Datasheet →ADC14C080CISQ/NOPB
✅ Drop-In✓ In Stock
$15.2 / Unit
View Datasheet →ADC14DS105AISQ/NOPB
✅ Drop-In✓ In Stock
$25.11 / Unit
View Datasheet →ADC12DC080CISQE/NOPB Maximum Ratings & Electrical Characteristics
| Number of Bits | 12 |
| Number of Inputs | 2 (simultaneous sampling) |
| Sampling Rate (Per Second) | 80 MSPS |
| Data Interface | Parallel (CMOS) |
| Architecture | Pipelined |
| Package / Case | 60-WFQFN Exposed Pad (9x9 mm, 0.5 mm pitch) |
| Package Code | HVQCCN / QCCN (LLP-60) |
| Operating Temperature | -40C to +85C (Industrial) |
| Supply Voltage (V A, V DR) | 3.0 V to 3.6 V |
| Supply Voltage Absolute Max | -0.3 V to 4.2 V |
| Voltage on Any Input Pin | -0.3 V to (V A + 0.3 V), not to exceed 4.2 V |
| Input Current at Any Pin | 5 mA max |
| Package Input Current | 50 mA max |
| Max Junction Temperature (T J) | +150C |
| Thermal Resistance (theta_JA) | 30 C/W |
| ESD Rating (HBM) | 2500 V |
| ESD Rating (Machine Model) | 250 V |
| Storage Temperature | -65C to +150C |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| RoHS Status | Compliant |
ADC12DC080CISQE/NOPB Pin Configuration
| Pin 1 | VINA+ — Channel A positive analog input |
| Pin 2 | VINA- — Channel A negative analog input (complement) |
| Pin 3 | VINA+ — Channel A positive analog input (alternate bond) |
| Pin 4 | VREF — Reference voltage bypass |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | VA — Analog 3.3V supply |
| Pin 7 | AGND — Analog ground |
| Pin 8 | CLK+ — Differential clock positive input |
| Pin 9 | CLK- — Differential clock negative input |
| Pin 10 | OE — Output enable (active low) |
| Pin 11 | PD — Power-down control |
| Pin 12 | DR — Data ready / clock output |
| Pin 13 | VINB+ — Channel B positive analog input |
| Pin 14 | VINB- — Channel B negative analog input (complement) |
| Pin 15 | VA — Analog 3.3V supply |
| Pin 16 | AGND — Analog ground |
| Pin 17 | DA0 — Channel A data output bit 0 (LSB) |
| Pin 18 | DA1 — Channel A data output bit 1 |
| Pin 19 | DA2 — Channel A data output bit 2 |
| Pin 20 | DA3 — Channel A data output bit 3 |
| Pin 21 | DA4 — Channel A data output bit 4 |
| Pin 22 | DA5 — Channel A data output bit 5 |
| Pin 23 | DA6 — Channel A data output bit 6 |
| Pin 24 | DA7 — Channel A data output bit 7 |
| Pin 25 | DA8 — Channel A data output bit 8 |
| Pin 26 | DA9 — Channel A data output bit 9 |
| Pin 27 | DA10 — Channel A data output bit 10 |
| Pin 28 | DA11 — Channel A data output bit 11 (MSB) |
| Pin 29 | VDR — Digital output driver 3.3V supply |
| Pin 30 | DGND — Digital ground |
| Pin 31 | DB0 — Channel B data output bit 0 (LSB) |
| Pin 32 | DB1 — Channel B data output bit 1 |
| Pin 33 | DB2 — Channel B data output bit 2 |
| Pin 34 | DB3 — Channel B data output bit 3 |
| Pin 35 | DB4 — Channel B data output bit 4 |
| Pin 36 | DB5 — Channel B data output bit 5 |
| Pin 37 | DB6 — Channel B data output bit 6 |
| Pin 38 | DB7 — Channel B data output bit 7 |
| Pin 39 | DB8 — Channel B data output bit 8 |
| Pin 40 | DB9 — Channel B data output bit 9 |
| Pin 41 | DB10 — Channel B data output bit 10 |
| Pin 42 | DB11 — Channel B data output bit 11 (MSB) |
| Pin 43 | VDR — Digital output driver 3.3V supply |
| Pin 44 | DGND — Digital ground |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | VINA- — Channel A negative input (alternate bond) |
| Pin 48 | VINA+ — Channel A positive input (alternate bond) |
| Pin 49 | VA — Analog 3.3V supply |
| Pin 50 | AGND — Analog ground |
| Pin 51 | VREF — Reference voltage bypass |
| Pin 52 | VCM — Common-mode voltage output |
| Pin 53 | VA — Analog 3.3V supply |
| Pin 54 | AGND — Analog ground |
| Pin 55 | VINB+ — Channel B positive input |
| Pin 56 | VINB- — Channel B negative input |
| Pin 57 | VINB+ — Channel B positive input (alternate bond) |
| Pin 58 | VINB- — Channel B negative input (alternate bond) |
| Pin 59 | AGND — Analog ground |
| Pin 60 | AGND — Analog ground |
Typical Applications
ADC12DC080CISQE/NOPB is suitable for 6 applications: Portable Ultrasound Imaging Front-End, I/Q Baseband Digitisation in Communications Receivers, Dual-Channel Data Acquisition Modules, Bench-Top Test and Measurement Instrumentation, Radar and Lidar Signal Capture, Medical Patient Monitoring Equipment.
Portable Ultrasound Imaging Front-End
The ADC12DC080CISQE/NOPB is well matched to portable ultrasound front-ends where 8 to 16 receive channels must be digitised at high speed. Its 80 MSPS per channel rate easily covers the 5-15 MHz band of harmonic imaging, and the dual matched channels simplify beamformer PCB layout. The 60-WQFN 9x9 mm footprint keeps the per-channel board area small, which is critical for handheld probes. Power dissipation at 80 MSPS fits within a battery-powered thermal budget, and the industrial -40C to +85C rating supports use near the patient interface. Engineers typically pair this ADC with a TI AFE5805 or AFE5808 analogue front-end and an FPGA such as XC7A35T-1FTG256C for beamforming.
Recommended
I/Q Baseband Digitisation in Communications Receivers
The dual 12-bit 80 MSPS architecture of the ADC12DC080CISQE/NOPB is well suited to I/Q baseband digitisation, where the I and Q channels of a quadrature demodulator must be captured simultaneously to preserve image rejection. The matched dual channels eliminate gain and offset mismatch that would otherwise corrupt the complex baseband signal. At 80 MSPS, the converter can capture baseband bandwidths up to 40 MHz, sufficient for narrowband LTE, 5G NR sub-6 GHz baseband, and many private-radio waveforms. The CMOS parallel output feeds directly into an FPGA or DSP, and the 3.3 V supply simplifies integration with low-power baseband processors.
Recommended
Dual-Channel Data Acquisition Modules
Industrial data-acquisition modules requiring simultaneous sampling on two channels benefit from the ADC12DC080CISQE/NOPB's dual 80 MSPS inputs. Applications include vibration analysis on rotating machinery, two-axis laser triangulation, and power-quality monitoring. The 12-bit resolution provides 72 dB of dynamic range, suitable for general-purpose digitisation. The 60-WQFN package with exposed pad gives 30 C/W thermal resistance, allowing continuous full-rate operation in sealed industrial enclosures. The parallel CMOS output simplifies connection to microcontrollers or FPGAs without needing an external serializer.
Recommended
Bench-Top Test and Measurement Instrumentation
Bench-top oscilloscopes, spectrum analysers, and arbitrary waveform digitiser platforms use the ADC12DC080CISQE/NOPB to capture two matched channels at 80 MSPS for time-domain and frequency-domain analysis. The dual channels are particularly useful in differential probing applications, where the two ADCs measure the plus and minus sides of a differential signal simultaneously. The 12-bit vertical resolution supports a 6.5-digit equivalent dynamic range in spectrum analysis, and the parallel output is easy to feed into a Spartan-7 or Kintex-7 FPGA for FFT processing. Industrial -40C to +85C grading eliminates the need for additional thermal compensation in lab environments.
Recommended
Radar and Lidar Signal Capture
Short-range automotive radar and lidar front-ends use the ADC12DC080CISQE/NOPB to capture two matched I/Q channels at intermediate frequency. The 80 MSPS rate supports IF bandwidths up to 40 MHz, suitable for FMCW radar chirps of several hundred MHz of bandwidth at baseband. The 12-bit resolution is acceptable for short-range object detection, and the low-latency pipelined architecture provides deterministic sampling delay across the channel pair. The 60-WQFN package keeps the BOM small for compact sensor modules.
Recommended
Medical Patient Monitoring Equipment
Patient monitors and ECG/EEG acquisition boards requiring two simultaneous channels of high-speed digitisation can use the ADC12DC080CISQE/NOPB for capturing biosignals with high temporal resolution. While clinical ECG itself is far slower than 80 MSPS, oversampling improves effective ENOB and enables digital filtering for 50/60 Hz line-noise rejection. The industrial temperature range and 60-WQFN footprint with exposed pad support compact, sealed medical enclosures. The CMOS parallel output is straightforward to interface with low-power processors used in portable medical devices.
Recommended
Recommended Products Summary
Engineering reference data for ADC12DC080CISQE/NOPB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC12C105CISQ | ADC12DC080CISQ | ADC14DS080CISQ/NOPB | ADC14DS105CISQE/NOPB | ADC14C080CISQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments (National Semi legacy) | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WQFN Exposed Pad (9x9 mm) | 60-WQFN - same | 60-WQFN - same | 60-WQFN - same | 60-WQFN - same | 60-WQFN - same |
| Resolution | 12 bit | 12 bit | 12 bit | 14 bit | 14 bit | 14 bit |
| Sampling Rate | 80 MSPS | 105 MSPS | 80 MSPS | 80 MSPS | 105 MSPS | 80 MSPS |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 | 1 |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| RoHS / Lead-Free | Yes (/NOPB suffix) | Yes | Tin-lead (non-NOPB) | Yes | Yes | Yes |
Key Differentiators
- Dual matched 80 MSPS channels in 60-WQFN (vs ADS8482IBRGZR (SAR, single-channel, ~250 kSPS))
- Higher sample rate than 12-bit baseline (vs ADC12C105CISQ)
- Lower resolution, lower cost than 14-bit family (vs ADC14DS080CISQ/NOPB)
Design Notes
Place the analog input coupling capacitors within 2 mm of the VINA+/VINA- and VINB+/VINB- pins and use a continuous analog ground plane on the top layer under the WQFN exposed pad. According to the ADC12DC080 datasheet, the exposed pad must be soldered to a copper pour of at least 1 square inch to maintain the 30 C/W thermal resistance figure; a starved thermal pad will cause the junction temperature to climb and degrade SNR at full 80 MSPS. Keep the parallel CMOS data bus traces short and length-matched between channels to preserve channel-to-channel skew.
The ADC12DC080 requires a low-jitter clock source - aim for less than 1 ps RMS jitter to preserve SNR at 80 MSPS. SNR degrades as 20*log10(1 / (2*pi*fin*tjitter)), so a 30 MHz input with 5 ps jitter loses about 4.5 dB of SNR versus a 1 ps source. Use a dedicated clock buffer or a low-jitter crystal oscillator placed close to the CLK+/CLK- pins, and route the clock differential pair with 100 ohm impedance and matched length.
Estimated: at 80 MSPS dual-channel, the VA supply current is approximately 100 mA, so add a ferrite bead and 10 uF + 0.1 uF ceramic decoupling on each VA pin. According to the datasheet, V A and V DR must be brought up together; sequencing them out of order can trigger input protection diodes. Place the 0.1 uF capacitors within 1 mm of each supply pin to minimise supply noise coupling into the analog front-end.
Do not drive the analog inputs above V A + 0.3 V or below -0.3 V; the datasheet absolute maximum is 5 mA into any analog pin. Avoid using long cable harnesses to the analog inputs - the high input bandwidth couples noise directly into the converter. When evaluating the ADC12DC080, use the National Semiconductor ADC12DC080LFEB evaluation board rather than a hand-wired prototype, as controlled-impedance analog traces are essential at 80 MSPS.
Compliance Information
RoHS compliant per /NOPB suffix in MPN. Industrial -40C to +85C temperature grade, not AEC-Q100. ESD HBM 2500 V, Machine Model 250 V per datasheet.
