AT28C040-20BC - 4Mbit Parallel EEPROM 200ns 32-CDIP | Microchip
부품 번호: AT28C040-20BC ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.4 | $254.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.5 | $9,750.00 |
| 1,000 | $17.2 | $17,200.00 |
AT28C040-20BC 개요
A parallel EEPROM is a non-volatile memory device that retains data without power and is accessed via a parallel data bus (8 bits per cycle in this case). Within the broader memory taxonomy, the AT28C040 sits as a byte-alterable EEPROM, a category below flash memory in write granularity but offering superior endurance for byte-level updates and a write-cycle model that behaves like static RAM without external components. It is part of the AT28C parallel EEPROM family, predecessors of modern serial flash in most new designs but still preferred where in-system reprogrammability, byte-write flexibility, and parallel throughput are required.
Key specifications include 4 Mbit density organized as 524,288 words x 8 bits, 200 ns access time, 256-byte page register for page-mode writes, 10 ms write cycle time per byte or page, 4.5 V to 5.5 V single-supply operation, and 440 mW maximum active power dissipation. The device supports read, byte-write, and page-write modes, with internal latch and software data protection mechanisms to prevent inadvertent writes.
Technically, the AT28C040 employs a CMOS EEPROM cell array with on-chip high-voltage generation for the Fowler-Nordheim tunneling write process. The integrated 256-byte page register allows up to 256 bytes to be loaded and then written simultaneously, substantially accelerating bulk programming relative to byte-write EEPROMs. The -20 speed grade denotes the 200 ns access time bin, and the BC suffix identifies the 32-pin side-brazed ceramic DIP package with a transparent quartz window for in-circuit UV erasure.
Typical applications include legacy industrial controllers, telecom equipment firmware storage, point-of-sale terminals, avionics instrumentation data logging, and embedded boot/program memory where parallel bus interface simplifies host integration.
When designing with this part, derate access time for capacitive bus loading and place 0.1 uF decoupling capacitors near the VCC pins. The UV-erasable window allows factory re-programming, but in-system byte-writes do not require erasure. Use the JEDEC-standard 32-CDIP footprint to ensure compatibility with legacy sockets and PCBs.
This page synthesizes distributor stock, parametric specifications, drop-in alternative candidates, and practical design notes beyond the datasheet itself, enabling engineers to evaluate, source, and integrate the AT28C040-20BC with confidence.
드롭인 대체품: AT28C040-20BC — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AT28C040-15BC
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
AT28C040-25BC
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
AT28C040-20BC 최대 정격 & 전기적 특성
| 메모리 유형 | Non-Volatile EEPROM (Parallel) |
| Memory Density | 4 Mbit (4194 kbit) |
| Memory Organization | 512K x 8 (524,288 words x 8 bits) |
| Bus Interface | Parallel |
| Access Time | 200 ns |
| Write Cycle Time | 10 ms (byte/page) |
| Page Register Size | 256 bytes |
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| Active Power Dissipation | 440 mW (max) |
| 패키지 | 32-CDIP (0.600 inch, 15.24 mm) Windowed Ceramic DIP |
| 실장 유형 | Through-Hole (THD) |
AT28C040-20BC 핀 구성
| 핀 1 | NC — Not connected (per datasheet) |
| 핀 2 | A18 — Address line 18 (MSB) |
| 핀 3 | A17 — Address line 17 |
| 핀 4 | A16 — Address line 16 |
| 핀 5 | A15 — Address line 15 |
| 핀 6 | A14 — Address line 14 |
| 핀 7 | A13 — Address line 13 |
| 핀 8 | A12 — Address line 12 |
| 핀 9 | VCC — Power supply (4.5 V to 5.5 V) |
| 핀 10 | WE — Write Enable (active low) |
| 핀 11 | OE — Output Enable (active low) |
| 핀 12 | A11 — Address line 11 |
| 핀 13 | A10 — Address line 10 |
| 핀 14 | A9 — Address line 9 |
| 핀 15 | A8 — Address line 8 |
| 핀 16 | A7 — Address line 7 |
| 핀 17 | A6 — Address line 6 |
| 핀 18 | A5 — Address line 5 |
| 핀 19 | A4 — Address line 4 |
| 핀 20 | A3 — Address line 3 |
| 핀 21 | A2 — Address line 2 |
| 핀 22 | A1 — Address line 1 |
| 핀 23 | A0 — Address line 0 (LSB) |
| 핀 24 | CE — Chip Enable (active low) |
| 핀 25 | GND — Ground |
| 핀 26 | I/O0 — Data I/O 0 (LSB) |
| 핀 27 | I/O1 — Data I/O 1 |
| 핀 28 | I/O2 — Data I/O 2 |
| 핀 29 | I/O3 — Data I/O 3 |
| 핀 30 | I/O4 — Data I/O 4 |
| 핀 31 | I/O5 — Data I/O 5 |
| 핀 32 | I/O6 — Data I/O 6 |
일반적인 애플리케이션
AT28C040-20BC 적합 용도: 6 애플리케이션s: Legacy Industrial Controller Firmware Storage, Telecom Equipment Boot and Configuration Memory, Avionics Instrumentation Data Logging Memory, Point-of-Sale Terminal Transaction Storage, Embedded Boot and Firmware Memory, Test and Measurement Calibration Tables.
Legacy Industrial Controller Firmware Storage
The AT28C040-20BC's 4 Mbit density, 200 ns parallel access, and 32-CDIP windowed ceramic package make it ideal for legacy industrial PLC and CNC controller firmware storage. Industrial controllers running 8051, 68k, or similar 8/16-bit host CPUs at 10-25 MHz need a non-volatile program store that keeps code execution deterministic without the erase-before-write penalty of flash. The 256-byte page register allows field firmware upgrades of up to 256 bytes per 10 ms write cycle, enabling modular updates over the controller's service port. Operating from 4.5 V to 5.5 V, the device tolerates 5 V industrial supply rails with 10% derating. The windowed ceramic DIP supports factory reprogramming during commissioning, while the parallel bus eliminates the firmware-loading overhead of serial EEPROMs in time-critical boot paths.
추천
Telecom Equipment Boot and Configuration Memory
The AT28C040-20BC's 4 Mbit parallel EEPROM density and 200 ns access time suit telecom equipment boot ROM and configuration parameter storage where reliability over decades of service is mandatory. Telecom switches, PBX systems, and base station controllers historically used parallel EEPROMs for boot code and provisioned parameters because the byte-write granularity and high write endurance far exceed flash NOR at the time of original design. The 32-CDIP socketed footprint allows field replacement without desoldering, a key requirement for legacy telecom infrastructure still in service. The 4.5 V to 5.5 V supply range aligns with telecom -48 V systems stepped down through traditional 5 V regulators. The parallel bus allows zero wait-state execution of boot code from the AT28C040 at clock rates up to 25 MHz, eliminating boot loader complexity.
추천
Avionics Instrumentation Data Logging Memory
The AT28C040-20BC is well-suited for avionics instrumentation data logging memory where non-volatile storage of flight parameters, fault logs, and calibration tables is required over decades of service. Avionics systems require byte-level write granularity and high write endurance (typically 100k cycles per byte) which the AT28C040's parallel EEPROM cell structure delivers. The 32-CDIP ceramic windowed package is preferred in avionics for hermeticity and resistance to humidity/moisture ingress over long service intervals. The 200 ns access allows direct parallel connection to avionics data buses without wait states. With 4 Mbit of capacity, the AT28C040 stores hundreds of flight hours of parametric data at typical logging rates. The windowed package permits factory reprogramming of calibration tables during scheduled maintenance.
추천
Point-of-Sale Terminal Transaction Storage
The AT28C040-20BC's 4 Mbit parallel EEPROM density and byte-write flexibility suit point-of-sale (POS) terminal transaction storage and terminal configuration memory. POS terminals require non-volatile storage of terminal ID, merchant keys, and recent transaction audit logs that survive power cycles and tamper events. The 200 ns access time allows the AT28C040 to sit directly on the terminal's 8-bit data bus with zero wait states at typical 8051 or 68k host clock rates. The 256-byte page write accelerates bulk configuration uploads during terminal commissioning. Operating from 4.5 V to 5.5 V with 440 mW max dissipation, the device integrates easily into legacy POS power architectures. The 32-CDIP socketed package allows field swap without board rework, valuable for installed-base service.
추천
Embedded Boot and Firmware Memory
The AT28C040-20BC provides 4 Mbit of non-volatile parallel memory for embedded systems requiring deterministic boot and large firmware images. Embedded systems that boot directly from ROM execute code in place (XIP) from the AT28C040 with zero shadowing latency, eliminating the bootloader complexity required when booting from serial flash. The 200 ns access time supports host bus clocks up to 25 MHz with no wait states, while the byte-write and 256-byte page-write modes allow field firmware updates without external programming voltage. With a 32-CDIP windowed ceramic footprint, the AT28C040 integrates into legacy through-hole embedded designs and remains socketed for factory re-flashing. The 4.5 V to 5.5 V supply aligns with classic 5 V embedded power rails.
추천
Test and Measurement Calibration Tables
The AT28C040-20BC is well-matched to test and measurement instrumentation requiring non-volatile storage of calibration tables, sensor linearization coefficients, and instrument configuration. T&M instruments including digital multimeters, oscilloscopes, and signal generators use parallel EEPROM to store per-range calibration data that must persist across power cycles and battery backup intervals. The 200 ns access time enables the AT28C040 to be accessed directly by the instrument's measurement microcontroller without latency penalty. The 256-byte page-write mode accelerates factory calibration loading across multiple ranges. The 32-CDIP windowed package supports factory re-calibration by removing the chip, UV-erasing, and re-installing - or alternatively using byte/page writes in-system. The 4 Mbit capacity stores calibration for hundreds of measurement ranges with full derivatives.
추천
추천 제품 요약
엔지니어링 참조 데이터: AT28C040-20BC — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AT28C040-15BC | AT28C040-25BC | AT28C040-20JC |
|---|---|---|---|---|
| Package | 32-CDIP (0.600 inch, windowed) | 32-CDIP (0.600 inch, windowed) - same | 32-CDIP (0.600 inch, windowed) - same | 32-PLCC (plastic, non-windowed) - different |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Memory Density | 4 Mbit (512K x 8) | 4 Mbit (512K x 8) | 4 Mbit (512K x 8) | 4 Mbit (512K x 8) |
| Access Time | 200 ns | 150 ns (-25%) | 250 ns (+25%) | 200 ns |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Write Cycle Time | 10 ms (byte/page) | 10 ms (byte/page) | 10 ms (byte/page) | 10 ms (byte/page) |
| UV-Erasable Window | Yes (ceramic windowed) | Yes (ceramic windowed) | Yes (ceramic windowed) | No (plastic PLCC, OTP-style) |
| Mounting Type | Through-Hole (DIP socket) | Through-Hole (DIP socket) | Through-Hole (DIP socket) | Surface-Mount (PLCC) |
| Active Power Dissipation | 440 mW (max) | 440 mW (max) | 440 mW (max) | 440 mW (max) |
| Page Register Size | 256 bytes | 256 bytes | 256 bytes | 256 bytes |
주요 차별점
- UV-erasable ceramic windowed package for factory reprogramming (vs AT28C040-20JC)
- 200 ns access time at the middle of the AT28C040 speed grade range (vs AT28C040-15BC)
- Through-hole DIP socket compatibility for legacy field serviceability (vs AT28C040-20JC)
설계 노트
Place a 0.1 uF decoupling capacitor as close as possible to the VCC pin (pin 9) to suppress high-frequency noise on the 5 V supply rail. Add a bulk 1 uF to 10 uF tantalum or ceramic capacitor on the same rail near the IC. The AT28C040 draws up to 440 mW active power during the 10 ms write cycle; ensure the 5 V regulator can supply the inrush without sagging below 4.5 V minimum.
Route the parallel address and data bus with matched trace lengths to minimize skew, especially for the lower address bits A0-A7 which toggle most frequently. Keep CE, OE, and WE control traces short and away from the data bus to avoid coupling. Use a ground plane beneath the device to provide a low-impedance return path for switching currents during read/write cycles.
Do not attempt to write the AT28C040 without first raising CE and lowering WE in the correct sequence per the datasheet write cycle timing diagram. Always observe the maximum 10 ms write cycle time before initiating the next operation. Polling the I/O pins for the Data# Poll or Toggle Bit ready status is the recommended method to detect write completion without fixed delays.
The 200 ns access time assumes a standard load of 100 pF. For heavily loaded buses or long PCB traces, derate access time or insert one wait state in the host CPU. Add 10 kohm pull-up resistors on the control inputs (CE, OE, WE) to prevent floating inputs from causing spurious writes during power-up transients.
규정 준수 정보
Compliance information not present in verified web data. The 32-CDIP ceramic windowed package is a legacy through-hole form factor that historically pre-dates RoHS standardization; engineers should confirm RoHS status with Microchip directly for new designs in RoHS-restricted regions.
