DP83869HMRGZR - High-Immunity Gigabit Ethernet PHY | TI
부품 번호: DP83869HMRGZR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $6.95 | $6.95 |
| 10 | $6.25 | $62.50 |
| 100 | $5.55 | $555.00 |
| 500 | $4.95 | $2,475.00 |
| 1,000 | $4.4 | $4,400.00 |
| 2,000 | $3.95 | $7,900.00 |
DP83869HMRGZR 개요
An Ethernet PHY (Physical Layer transceiver) is the interface IC that connects a MAC (Media Access Controller) to the physical copper or fiber cable, handling line coding, link training, echo/return-loss compensation, and clock/data serialization. As part of the Physical Layer transceiver -> Ethernet transceiver -> Network Interface IC -> Power Management/Connectivity IC hierarchy, gigabit PHYs sit one layer below the MAC and one layer above the magnetics/RJ-45 (or SFP fiber cage), translating MII/GMII/RGMII parallel data into differential serial signals compliant with IEEE 802.3 10/100/1000BASE-T.
Key features of the DP83869HMRGZR include: IEEE 802.3 10/100/1000 Mbps operation, integrated PMD sublayers for copper and fiber, RGMII/MII/GMII MAC interfaces, media-conversion between copper and fiber ports, AEC-Q100-qualified extended-temperature grade (-40C to +125C), low-latency cut-through mode, and 8 kV IEC 61000-4-2 ESD protection (direct contact). The 48-pin VQFN (RGZ) package exposes a thermal pad for heat dissipation and supports reflow soldering on standard industrial PCB processes.
Architecturally, the DP83869HMRGZR integrates the entire physical coding sublayer (PCS), physical medium attachment (PMA), and physical medium dependent (PMD) blocks on-chip, eliminating the need for external PHY magnetics tuning circuits. The device supports both SGMI and RGMII host interfaces with selectable timing modes, and includes integrated termination resistors that simplify the BOM. Cable diagnostics, loopback modes, and jumbo-frame support extend its utility in industrial Ethernet switches.
Typical applications include industrial Ethernet switches, factory automation controllers, motor-drive communication boards, 5G small-cell fronthaul, automotive Ethernet gateways, and fiber-to-copper media converters. The wide temperature and high immunity make it well suited for IEC 61000-4 industrial EMC environments where standard PHYs would fail conformance.
When designing with this part, ensure the MDI traces are 100-ohm differential with controlled 50-ohm single-ended impedance, place the 1.8V/2.5V/3.3V decoupling capacitors within 2 mm of each supply pin, and use a 4-layer PCB with a continuous ground plane below the PHY to meet IEEE 802.3 return-loss masks.
This page synthesizes distributor pricing, drop-in TI same-family alternatives, design notes, and an honest comparison against cross-brand gigabit PHYs - content not aggregated on any single manufacturer or distributor page.
드롭인 대체품: DP83869HMRGZR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: DP83869HMRGZR (동일 폼 팩터 및 풋프린트) — 차이점: Package, Cable Diagnostics, MAC Interface, MSL Level, Product Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
DP83869HMRGZT
✅ 드롭인✓ 재고 있음
$9.3 / 개
데이터시트 보기 →DP83867ERGZR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83867IRPAPT
✅ 드롭인✓ 재고 있음
$5.4 / 개
데이터시트 보기 →DP83867CSRGZT
✅ 드롭인✓ 재고 있음
$8.4 / 개
데이터시트 보기 →DP83869HMRGZR-Q1
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83869HMRGZR 사양
| Product Type | Ethernet PHY transceiver (10/100/1000 Mbps) |
| Supported Protocols | 10BASE-Te, 100BASE-TX, 1000BASE-T (copper); 100BASE-FX, 1000BASE-X (fiber) |
| MAC Interface | RGMII / MII / GMII |
| 공급 전압 | 1.8 V / 2.5 V / 3.3 V |
| 패키지 | 48-VQFN (RGZ) 7x7 mm with exposed thermal pad |
| 동작 온도 | -40 C to +125 C (extended industrial) |
| ESD Protection | 8 kV IEC 61000-4-2 (direct contact) |
| Media Conversion | Supported (copper <-> fiber) |
| Cable Diagnostics | Built-in TDR-based cable analysis |
| Jumbo Frame Support | Yes |
| Loopback Modes | Yes (near-end and far-end) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
| MSL 레벨 | 2 (per JEDEC J-STD-020) |
DP83869HMRGZR 핀 구성
| 핀 1 | VDDIO — I/O supply (2.5 V or 3.3 V) |
| 핀 2 | TX_CLK — RGMII transmit clock (to MAC) |
| 핀 3 | TX_D0 — RGMII transmit data 0 |
| 핀 4 | TX_D1 — RGMII transmit data 1 |
| 핀 5 | TX_D2 — RGMII transmit data 2 |
| 핀 6 | TX_D3 — RGMII transmit data 3 |
| 핀 7 | TX_EN — RGMII transmit enable / control |
| 핀 8 | RX_CLK — RGMII receive clock (from MAC) |
| 핀 9 | RX_D0 — RGMII receive data 0 |
| 핀 10 | RX_D1 — RGMII receive data 1 |
| 핀 11 | RX_D2 — RGMII receive data 2 |
| 핀 12 | RX_D3 — RGMII receive data 3 |
| 핀 13 | RX_DV — RGMII receive data valid |
| 핀 14 | MDIO — Management data I/O |
| 핀 15 | MDC — Management data clock |
| 핀 16 | INT — Interrupt output (open-drain) |
| 핀 17 | RESET — Hardware reset, active-low |
| 핀 18 | XI — 25 MHz crystal input |
| 핀 19 | XO — 25 MHz crystal output |
| 핀 20 | GND — Ground |
| 핀 21 | VDD — 1.8 V core supply |
| 핀 22 | LED0 — Link/activity LED indicator |
| 핀 23 | LED1 — Speed LED indicator |
| 핀 24 | LED2 — Link status LED indicator |
| 핀 25 | JTAG_TCK — JTAG test clock |
| 핀 26 | JTAG_TMS — JTAG test mode select |
| 핀 27 | JTAG_TDI — JTAG test data in |
| 핀 28 | JTAG_TDO — JTAG test data out |
| 핀 29 | SREFCLK — SerDes reference clock |
| 핀 30 | SD_P — SerDes fiber differential positive |
| 핀 31 | SD_N — SerDes fiber differential negative |
| 핀 32 | MDI_P0 — 1000BASE-T differential pair 0 positive |
| 핀 33 | MDI_N0 — 1000BASE-T differential pair 0 negative |
| 핀 34 | MDI_P1 — 1000BASE-T differential pair 1 positive |
| 핀 35 | MDI_N1 — 1000BASE-T differential pair 1 negative |
| 핀 36 | MDI_P2 — 1000BASE-T differential pair 2 positive |
| 핀 37 | MDI_N2 — 1000BASE-T differential pair 2 negative |
| 핀 38 | MDI_P3 — 1000BASE-T differential pair 3 positive |
| 핀 39 | MDI_N3 — 1000BASE-T differential pair 3 negative |
| 핀 40 | AVDD — Analog supply (2.5 V) |
| 핀 41 | AVDDH — Analog high-voltage supply (3.3 V) |
| 핀 42 | AGND — Analog ground |
| 핀 43 | NC — Not connected (per datasheet) |
| 핀 44 | NC — Not connected (per datasheet) |
| 핀 45 | NC — Not connected (per datasheet) |
| 핀 46 | NC — Not connected (per datasheet) |
| 핀 47 | NC — Not connected (per datasheet) |
| 핀 48 | THERMAL_PAD — Exposed thermal pad, connect to ground |
일반적인 애플리케이션
DP83869HMRGZR 적합 용도: 7 애플리케이션s: Industrial Ethernet Switch, Motor Drive Communication Board, 5G Small-Cell Fronthaul Gateway, Automotive Ethernet Gateway, Fiber-to-Copper Media Converter, Test & Measurement Ethernet Tap, Industrial IoT Edge Gateway.
Industrial Ethernet Switch
The DP83869HMRGZR serves as the 1G copper/fiber uplink PHY in managed industrial switches. Its 8 kV IEC 61000-4-2 ESD immunity and -40C to +125C operating range exceed IEC 61850-3 / IEEE 1613 substation EMC requirements, where consumer-grade PHYs would fail. The integrated 1000BASE-X SerDes connects directly to SFP cages without an external converter, lowering BOM. RGMII host interface connects to the switch MAC ASIC.
추천
Motor Drive Communication Board
Variable-frequency drives and servo controllers use the DP83869HMRGZR to expose EtherNet/IP, PROFINET, or EtherCAT industrial Ethernet ports. The high-immunity design withstands 8 kV ESD events and fast transient bursts common on motor-drive PCBs with high dV/dt switching. The -40C to +125C temperature grade covers cabinet-internal conditions, and the 48-VQFN (RGZ) footprint keeps the analog section compact.
추천
5G Small-Cell Fronthaul Gateway
Small-cell base stations use the DP83869HMRGZR to bridge the baseband SoC to fiber uplinks running 1000BASE-X to the DU/CU. The integrated PMD eliminates an external SFP-PHY chip, and cut-through mode keeps latency low for fronthaul timing budgets. The RGMII host interface is supported by small-cell SoCs including TI's own KeyStone processors.
추천
Automotive Ethernet Gateway
In-vehicle networking gateways use the DP83869HMRGZR (or its -Q1 automotive-grade variant) to bridge 100BASE-T1/1000BASE-T1 PHYs to the central compute SoC. The AEC-Q100 qualified grade ensures operation in -40C to +125C cabin and engine-bay environments. The integrated cable diagnostics detect open and shorted MDI pairs during assembly, simplifying ECU production test.
추천
Fiber-to-Copper Media Converter
Standalone media converters use the DP83869HMRGZR to bridge a fiber SFP uplink to a copper RJ-45 downlink. The integrated media-conversion engine eliminates an external converter ASIC, reducing the BOM to a single PHY plus magnetics and SFP cage. The 8 kV IEC 61000-4-2 ESD on copper MDI protects against field-installation transients.
추천
Test & Measurement Ethernet Tap
Network monitoring taps use the DP83869HMRGZR in a passive bridge configuration with near-end and far-end loopback modes to inline-monitor gigabit links without disrupting traffic. The low-latency cut-through mode preserves packet timing for accurate jitter measurement, and the RGMII host interface drops into FPGA-based TAP cards.
추천
Industrial IoT Edge Gateway
Edge gateways aggregating field-bus traffic onto an enterprise uplink use the DP83869HMRGZR as the 1G uplink PHY. The fiber support allows deployment in large factory floors with EMI-heavy environments where copper-only links would be unreliable. Combined with a microcontroller host running Linux, it forms a complete industrial IIoT edge node.
추천
추천 제품 요약
엔지니어링 참조 데이터: DP83869HMRGZR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DP83869HMRGZT | DP83867ERGZR | DP83867IRPAPT | DP83867CSRGZT | DP83869HMRGZR-Q1 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) - same family | 48-VQFN (RGZ) - same family | 48-VQFN (RGZ) - same family | 48-VQFN (RGZ) 7x7 mm - same |
| Max Speed | 1000 Mbps (copper and fiber) | 1000 Mbps (copper and fiber) | 1000 Mbps (copper only) | 1000 Mbps (copper only) | 1000 Mbps (copper only) | 1000 Mbps (copper and fiber) |
| Fiber Support | Yes (100BASE-FX, 1000BASE-X) | Yes | No | No | No | Yes |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +85 C (industrial) | 0 C to +70 C | -40 C to +125 C |
| MAC Interface | RGMII / MII / GMII | RGMII / MII / GMII | RGMII / MII / GMII | RGMII | RGMII | RGMII / MII / GMII |
| AEC-Q100 Qualified | Industrial (verify with TI for -Q1) | Industrial | Industrial | Industrial | Commercial | Yes (AEC-Q100) |
주요 차별점
- Integrated fiber (1000BASE-X/100BASE-FX) SerDes (vs DP83867ERGZR)
- 8 kV IEC 61000-4-2 direct-contact ESD immunity (vs DP83867 family)
- Extended-temperature operation -40C to +125C (vs DP83867CSRGZT (commercial 0C to +70C))
- AEC-Q100 automotive-grade option (vs DP83869HMRGZR (industrial))
설계 노트
Route MDI differential pairs (pins 32-39) as 100-ohm differential impedance with intra-pair skew under 50 mil, and place the common-mode choke within 25 mm of the RJ-45 magnetics. Use a continuous ground plane directly below the MDI traces to meet IEEE 802.3 return-loss masks. Decoupling caps (100 nF + 1 uF) must be placed within 2 mm of each supply pin.
Keep the 25 MHz crystal (XI/XO, pins 18-19) within 5 mm of the PHY with a guard ring tied to analog ground. Avoid routing digital RGMII signals under the crystal or across the analog ground split. The exposed thermal pad (pin 48) must be soldered to a grounded copper pour of at least 1 square inch to meet the package thermal resistance specified in the datasheet.
Magnetics must meet IEEE 802.3 isolation requirements (1500 VAC). For IEC 61000-4-2 8 kV ESD compliance, place an external TVS diode array (e.g., PESD0402-140) within 5 mm of the RJ-45 connector. Common-mode chokes on each MDI pair are recommended for industrial EMC conformance. Reference TI's SNLA285 EMC layout application note for component placement guidance.
Do not leave NC pins floating - the DP83869HM datasheet requires NC pins (43-47) to be left unconnected on the PCB but routed to a no-connect pad for manufacturing. Avoid using a 3.3V supply on VDDIO when the host MAC is 1.8V (use level shifters or configure the MAC to 2.5V instead). Crystal load capacitors must be sized per the crystal datasheet, not guessed at 12 pF.
RGMII signals use source-synchronous clocking; the TX_CLK skew to TX_D[3:0] must be within 500 ps. Use matched trace lengths on the entire RGMII bus (within 25 mil tolerance). For GMII at 125 MHz, reduce trace length to 50 mm maximum to avoid exceeding rise-time budget. The JTAG pins (25-28) should be pulled to known states if unused (TCK low, TMS high) per IEEE 1149.1.
규정 준수 정보
RoHS and REACH compliant per TI product page. The standard DP83869HMRGZR is industrial-grade; the -Q1 suffix variant is AEC-Q100 qualified. Halogen-free status not explicitly stated in verified data.
