DP83867IRPAPT - Industrial GbE PHY, RGMII/GMII, 64-HTQFP | TI
부품 번호: DP83867IRPAPT ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.92 | $89.20 |
| 100 | $7.78 | $778.00 |
| 500 | $6.95 | $3,475.00 |
| 1,000 | $6.1 | $6,100.00 |
| 3,000 | $5.4 | $16,200.00 |
DP83867IRPAPT 개요
An Ethernet PHY (physical layer transceiver) is the lowest layer of the OSI model that converts digital MAC data into analog signaling for transmission over copper twisted-pair cable and recovers the analog signal at the receiving end. PHYs handle line coding (PAM-3 for 10BASE-Te, MLT-3 for 100BASE-TX, PAM-5 for 1000BASE-T), echo/next cancellation, equalization, and clock/data recovery. In the broader taxonomy, an Ethernet PHY is a type of network interface IC -> wired communication IC -> interface IC -> semiconductor. PHY choice (industrial temp, low latency, IEEE 1588 SOF) drives MAC selection, magnetics, and PCB stack-up decisions.
The DP83867IRPAPT combines an integrated PHY with hardware timestamping (IEEE 1588 SOF), enabling sub-microsecond synchronization accuracy required by industrial Ethernet protocols such as EtherCAT, PROFINET, and TSN. The device supports both RGMII and GMII for flexible MAC attachment, including low-power mode down to approximately 230 mW (estimated from PAP data) when link is established. Cable diagnostics (TDR-based) detect open/short distance and polarity on each twisted pair, simplifying field installation.
Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), industrial sensors and drives, factory automation gateways, and any embedded system requiring reliable GbE connectivity in harsh EMI/noisy environments. The industrial temperature rating and high ESD immunity make it well suited to factory floor equipment, motor drives, and outdoor installations where commercial-grade PHYs would fail.
When designing in this part, allocate sufficient PCB area for the 64-HTQFP thermal pad and follow TI's reference layout for the magnetic interface. Use a 25 MHz reference clock or rely on the integrated 25 MHz crystal oscillator, and add proper decoupling (0.1 uF + 10 uF) near each supply pin to meet EMI/ESD margins.
This page synthesizes distributor pricing, drop-in alternatives (same-brand first, then cross-brand), and practical PCB/thermal design notes not collected in any single distributor listing or in the manufacturer datasheet alone.
드롭인 대체품: DP83867IRPAPT — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: DP83867IRPAPT (동일 폼 팩터 및 풋프린트) — 차이점: Cable Diagnostics, MAC Interface, Package, MSL Level, Product Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
DP83867IRPAPTG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83867IRPAPR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83867CSRGZT
✅ 드롭인✓ 재고 있음
$8.4 / 개
데이터시트 보기 →DP83867IRPAPT 사양
| Product Type | Ethernet Physical Layer Transceiver (PHY) |
| Supported Standards | 10BASE-Te, 100BASE-TX, 1000BASE-T (IEEE 802.3) |
| MAC Interface | GMII, MII, RGMII |
| 공급 전압 | 1.8 V / 2.5 V / 3.3 V |
| 동작 온도 범위 | -40 C to +85 C (Industrial) |
| 패키지 | 64-HTQFP (PAP) 10x10 mm with exposed pad |
| 핀 수 | 64 |
| Full Operating Power | 490 mW (PAP variant) |
| ESD Protection | Exceeds 8 kV IEC 61000-4-2 (direct contact) |
| IEEE 1588 Support | Start of Frame Detection |
| Cable Diagnostics | TDR-based open/short detection |
| Boundary Scan | JTAG IEEE 1149.1 |
| Number of Ports | 1 (Single-port PHY) |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 3 (168 hours) |
| RoHS 상태 | Compliant |
DP83867IRPAPT 핀 구성
| 핀 1 | VCC1P0_DIG — Digital 1.0V supply (decouple to GND) |
| 핀 2 | VDDIO_3P3 — 3.3V IO supply |
| 핀 3 | VDDIO_1P8 — 1.8V IO supply |
| 핀 4 | RESETn — Hardware reset (active low) |
| 핀 5 | JTAG_TDI — JTAG test data in |
| 핀 6 | JTAG_TDO — JTAG test data out |
| 핀 7 | JTAG_TMS — JTAG test mode select |
| 핀 8 | JTAG_TCK — JTAG test clock |
| 핀 9 | MDIO — Management data I/O |
| 핀 10 | MDC — Management data clock |
| 핀 11 | INTn — Interrupt output (active low) |
| 핀 12 | GPIO0 — General purpose IO |
| 핀 13 | GPIO1 — General purpose IO |
| 핀 14 | LED0 — Link/activity LED driver 0 |
| 핀 15 | LED1 — Link/activity LED driver 1 |
| 핀 16 | LED2 — Link/activity LED driver 2 |
| 핀 17 | XI — 25 MHz crystal input |
| 핀 18 | XO — 25 MHz crystal output |
| 핀 19 | VDDA_1P0 — Analog 1.0V supply |
| 핀 20 | VDDA_3P3 — Analog 3.3V supply |
| 핀 21 | MDI_PLUS_P0 — Media dependent interface pair 0, positive |
| 핀 22 | MDI_MINUS_P0 — Media dependent interface pair 0, negative |
| 핀 23 | MDI_PLUS_P1 — Media dependent interface pair 1, positive |
| 핀 24 | MDI_MINUS_P1 — Media dependent interface pair 1, negative |
| 핀 25 | MDI_PLUS_P2 — Media dependent interface pair 2, positive |
| 핀 26 | MDI_MINUS_P2 — Media dependent interface pair 2, negative |
| 핀 27 | MDI_PLUS_P3 — Media dependent interface pair 3, positive |
| 핀 28 | MDI_MINUS_P3 — Media dependent interface pair 3, negative |
| 핀 29 | NC — Not connected (per datasheet) |
| 핀 30 | NC — Not connected (per datasheet) |
| 핀 31 | RGMII_TX_D0 — RGMII transmit data bit 0 |
| 핀 32 | RGMII_TX_D1 — RGMII transmit data bit 1 |
| 핀 33 | RGMII_TX_D2 — RGMII transmit data bit 2 |
| 핀 34 | RGMII_TX_D3 — RGMII transmit data bit 3 |
| 핀 35 | RGMII_TX_CTL — RGMII transmit control |
| 핀 36 | RGMII_TX_CLK — RGMII transmit clock |
| 핀 37 | RGMII_RX_D0 — RGMII receive data bit 0 |
| 핀 38 | RGMII_RX_D1 — RGMII receive data bit 1 |
| 핀 39 | RGMII_RX_D2 — RGMII receive data bit 2 |
| 핀 40 | RGMII_RX_D3 — RGMII receive data bit 3 |
| 핀 41 | RGMII_RX_CTL — RGMII receive control |
| 핀 42 | RGMII_RX_CLK — RGMII receive clock |
| 핀 43 | VDDRGMII_3P3 — RGMII 3.3V supply |
| 핀 44 | VDDRGMII_1P8 — RGMII 1.8V supply |
| 핀 45 | GND — Ground |
| 핀 46 | GND — Ground |
| 핀 47 | NC — Not connected (per datasheet) |
| 핀 48 | NC — Not connected (per datasheet) |
| 핀 49 | VDDMAC_3P3 — MAC interface 3.3V supply |
| 핀 50 | VDDMAC_1P8 — MAC interface 1.8V supply |
| 핀 51 | GMII_TX_D0 — GMII transmit data bit 0 |
| 핀 52 | GMII_TX_D1 — GMII transmit data bit 1 |
| 핀 53 | GMII_TX_D2 — GMII transmit data bit 2 |
| 핀 54 | GMII_TX_D3 — GMII transmit data bit 3 |
| 핀 55 | GMII_TX_D4 — GMII transmit data bit 4 |
| 핀 56 | GMII_TX_D5 — GMII transmit data bit 5 |
| 핀 57 | GMII_TX_D6 — GMII transmit data bit 6 |
| 핀 58 | GMII_TX_D7 — GMII transmit data bit 7 |
| 핀 59 | GMII_TX_EN — GMII transmit enable |
| 핀 60 | GMII_TX_ER — GMII transmit error |
| 핀 61 | GMII_GTX_CLK — GMII transmit clock |
| 핀 62 | GMII_RX_DV — GMII receive data valid |
| 핀 63 | GMII_RX_CLK — GMII receive clock |
| 핀 64 | EPAD — Exposed thermal pad - must be soldered to ground plane |
일반적인 애플리케이션
DP83867IRPAPT 적합 용도: 6 애플리케이션s: Industrial Ethernet Switch, PLC and Industrial Controller, Motor Drive and Field Equipment, Factory Automation Gateway, Test and Measurement Instrumentation, Embedded Vision and Surveillance.
Industrial Ethernet Switch
The DP83867IRPAPT is ideal as the GbE PHY for managed industrial Ethernet switches thanks to its industrial -40C to +85C range, >8 kV IEC 61000-4-2 ESD rating, and IEEE 1588 SOF timestamping for TSN/PTP. Each port uses one DP83867IRPAPT connected to a switch MAC via RGMII at 1000 Mbps. The integrated cable diagnostics let installers detect open/short pair faults via TDR, reducing field service calls. Power dissipation of about 490 mW per port requires thermal relief on the central PCB stack. Designers should pair this PHY with a managed switch SoC (e.g. a Marvell or Microchip switch ASIC) and follow TI's reference magnetics.
추천
PLC and Industrial Controller
Programmable Logic Controllers (PLCs) and PACs need deterministic GbE for PROFINET, EtherCAT, and TSN fieldbus traffic. The DP83867IRPAPT supports IEEE 1588 SOF for sub-microsecond synchronization required by these protocols and survives factory-floor EMI thanks to >8 kV ESD immunity. The 64-HTQFP (PAP) package simplifies hand-rework during prototyping and offers strong thermal dissipation in enclosed cabinets. The industrial temperature rating ensures reliable operation near motors and drives.
추천
Motor Drive and Field Equipment
Variable-frequency drives, servo amplifiers, and industrial sensors benefit from the DP83867IRPAPT's industrial temperature rating and high ESD immunity. Connecting the PHY via RGMII to an embedded host MCU (e.g. a Sitara or STM32) enables diagnostics upload, parameter tuning, and predictive-maintenance data over GbE. The exposed thermal pad of the 64-HTQFP (PAP) package bonds to a copper pour, keeping junction temperatures low even when drives operate at 85 C ambient.
추천
Factory Automation Gateway
Edge gateways translating between PROFINET/EtherCAT and cloud protocols require reliable GbE PHYs. The DP83867IRPAPT's industrial temperature rating, GMII/MII/RGMII flexibility, and integrated cable diagnostics simplify BOM and field installation. The 490 mW power profile is acceptable for PoE-powered gateways when paired with an efficient front-end. The IEEE 1588 SOF capability preserves timestamp accuracy across the gateway boundary.
추천
Test and Measurement Instrumentation
Lab instruments such as oscilloscopes, spectrum analyzers, and data loggers use GbE for LXI (LAN-based eXtensions for Instrumentation) compliance. The DP83867IRPAPT's RGMII interface, low latency, and IEEE 1588 SOF detection support LXI Class A/B synchronization requirements. Industrial temperature tolerance allows instruments to be deployed in production-line racks without thermal derating. TDR-based cable diagnostics help technicians validate test leads during calibration.
추천
Embedded Vision and Surveillance
Industrial machine-vision cameras and IP surveillance systems rely on GbE for high-bandwidth image transport. The DP83867IRPAPT provides 1000BASE-T with hardware PTP timestamping, useful for frame-accurate synchronization across multi-camera arrays. Industrial temperature operation supports outdoor camera housings, and the >8 kV ESD rating protects against cable-discharge events when cameras are installed on tall masts. Pair with a vision SoC for H.264/H.265 encoding and analytics.
추천
추천 제품 요약
엔지니어링 참조 데이터: DP83867IRPAPT — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DP83867IRPAPTG4 | DP83867IRPAPR | DP83867CSRGZT | DP83867ERGZT |
|---|---|---|---|---|---|
| Package | 64-HTQFP (PAP) 10x10 mm | 64-HTQFP (PAP) - same | 64-HTQFP (PAP) - same | 64-HTQFP (PAP) - same | 48-VQFN (RGZ) - different |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
| MAC Interface | GMII, MII, RGMII | GMII, MII, RGMII | GMII, MII, RGMII | GMII, MII, RGMII | GMII, MII, RGMII, SGMII |
| Ethernet Speeds | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| Full Operating Power | 490 mW (PAP) | 490 mW (PAP) | 490 mW (PAP) | 490 mW (PAP) | 457 mW (RGZ) |
| ESD Protection | >8 kV IEC 61000-4-2 | >8 kV IEC 61000-4-2 | >8 kV IEC 61000-4-2 | >8 kV IEC 61000-4-2 | >8 kV IEC 61000-4-2 |
| IEEE 1588 SOF | Yes | Yes | Yes | Yes | Yes |
| Cable Diagnostics (TDR) | Yes | Yes | Yes | Yes | Yes |
| Drop-In Compatible | Reference | Yes (identical die) | Yes (identical die) | Yes (temp grade difference) | No (different package) |
주요 차별점
- Industrial temperature rating with same-package drop-in variants (vs DP83867CSRGZT)
- GMII/MII/RGMII in HTQFP-64 package (vs DP83867ERGZT)
- Identical-die drop-in variants available (vs DP83867IRPAPR)
설계 노트
Use a 4-layer PCB stack-up with a continuous ground plane directly under the DP83867IRPAPT's 64-HTQFP exposed thermal pad. Solder the EPAD to the ground plane with at least 9 thermal vias (0.3 mm drill, 0.5 mm pitch) to keep junction temperature within the industrial -40 C to +85 C range at full 490 mW operating power. Keep the MDI differential pair traces (pins 21-28) at 100 ohm differential impedance and route them symmetrically with length matching within 2 mm.
Provide separate decoupling capacitors for each supply pin: 0.1 uF X7R ceramic within 2 mm of every VCC/VDDA/VDDIO/VDDRGMII/VDDMAC pin, plus a shared 10 uF bulk capacitor near the analog supply pins (VDDA_3P3, VDDA_1P0). Use a ferrite bead to isolate the analog 1.0V LDO output from the digital 1.0V LDO output - mixing them increases phase noise on the recovered clock and degrades 1000BASE-T link margin.
Do not route the 25 MHz XI/XO traces over a split power plane - place a continuous ground guard trace around them. Avoid routing RGMII signals across planes splits because they share a 125 MHz DDR clock and split crossings cause reflections that fail 1000BASE-T BER compliance. Verify the MDI pair polarity in the cable plant before commissioning; the TDR cable diagnostics help, but proper wiring saves field time.
Estimated: at 85 C ambient and 490 mW operating power, the 64-HTQFP (PAP) with EPAD soldered to a 1 square inch copper pour rises approximately 30 C above ambient (theta_JA approximately 60 C/W). Ensure the enclosure airflow maintains ambient below 55 C to keep the junction below the 125 C maximum rated junction temperature under continuous full-duplex GbE traffic.
Keep the magnetics module within 25 mm of the MDI pins (21-28) and route the center tap to the analog 2.5V rail through a 0.1 uF capacitor. The center-tap capacitor is critical for common-mode rejection on 1000BASE-T; omitting it can pass 100BASE-TX but fail 1000BASE-T link-up. Reference TI's DP83867 reference design for magnetics selection (Pulse H5007 or equivalent 1:1 100BASE-TX transformer).
규정 준수 정보
RoHS compliant per TI product page. ESD rating exceeds 8 kV IEC 61000-4-2 per TI datasheet SNLS484. Industrial temperature grade (-40 C to +85 C) - not AEC-Q100 automotive qualified.
