DS90C365AMT - 3.3V 18-Bit LVDS FPD Transmitter | TI
부품 번호: DS90C365AMT ✓ 활성DS90C365AMT 개요
A Flat Panel Display Link transmitter is a display-interface IC that converts parallel logic signals into low-voltage differential signaling. This conversion reduces signal amplitude, supports clock-rate multiplication, and carries pixel and control data across a compact differential link. The DS90C365A family belongs to the broader category of display serializers and interface transceivers, placing it within the semiconductor and display-interface hierarchy.
The DS90C365AMT accepts 18-bit display data together with associated control and clock information and serializes the information into four LVDS lanes. Its programmable operation supports link configuration across different display architectures. The 87.5 MHz link frequency and 1.785 Gbps data capability make the device applicable to flat-panel displays, industrial LCD panels, digital signage, and other multi-pixel parallel-to-LVDS interfaces.
The DS90C365A incorporates a phase-locked loop that supports the high-speed serialization function. Because this is a transmitter-only device, it requires a compatible LVDS receiver at the other end of the link. The 48-TSSOP package provides 48 external terminals and is suitable for conventional surface-mount PCB assembly. Tube packaging is identified for the DS90C365AMT ordering variant in distributor search data.
Typical implementations connect a display timing controller or graphics source to an LVDS display panel. The transmitter accepts parallel pixels and control signals, then sends four differential lanes carrying serialized data and embedded clock information. The receiver determines the supported display timing and must be electrically compatible with the transmitter output. This arrangement is useful where a compact LVDS interface is required instead of a direct parallel interface across the full board or cable distance.
Designers should verify LVDS trace impedance, differential pair geometry, connector or panel requirements, receiver compatibility, and the power-supply decoupling network against the manufacturer datasheet. The stated 3 V to 3.6 V operating supply leaves little tolerance for supply overshoot, so routing and load behavior must be controlled. Pin assignments and unused-terminal details should be taken directly from the manufacturer documentation before PCB routing.
This page consolidates the verified manufacturer and distributor information for DS90C365AMT, identifies documented pin-compatible family replacements, and provides application guidance, comparison criteria, and design considerations. It also distinguishes verified performance figures from parameters that require confirmation from the complete manufacturer datasheet.
드롭인 대체품: DS90C365AMT — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
DS90C363BMTX
✅ 드롭인가격 문의
데이터시트 보기 →DS90C363A
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C365
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C363BMTX
✅ 드롭인가격 문의
데이터시트 보기 →DS90C365AMT 사양
| Product Type | Programmable LVDS flat-panel-display transmitter |
| 공급 전압 | 3 V to 3.6 V |
| Nominal Supply Voltage | +3.3 V |
| Input Data Width | 21 bits of LVCMOS/LVTTL data |
| Display Data Resolution | 18 bits |
| LVDS Output Channels | 4 differential data streams |
| Pixel Clock | 87.5 MHz |
| Aggregate Data Rate | 1.785 Gbps |
| Logic Input Levels | LVCMOS/LVTTL |
| Output Signal Type | Low-Voltage Differential Signaling (LVDS) |
| Clocking Architecture | Phase-locked loop |
| 패키지 | 48-TSSOP |
| 핀 수 | 48 pins |
| 실장 유형 | Surface mount |
| Shipping Package | Tube |
DS90C365AMT tube 핀 구성 가이드
DS90C365AMT(tube 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: DS90C365AMT.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DS90C365AMT 적합 용도: 6 애플리케이션s: Industrial LCD Panel Interface, Digital Signage Controller, Professional Video Monitor, Embedded Flat-Panel Display, Medical Display Interface, Test and Measurement Display.
Industrial LCD Panel Interface
The DS90C365AMT fits an industrial LCD panel that accepts an 18-bit parallel display input and a four-lane LVDS link. It accepts 21 bits of LVCMOS/LVTTL data and serializes that information at an 87.5 MHz pixel clock, producing an aggregate rate of 1.785 Gbps. This arrangement reduces the number of high-speed signal conductors crossing a display module boundary compared with carrying all parallel pixels directly. The transmitter should be paired with a compatible panel-side receiver and verified against the panel's lane, timing, and configuration requirements. Its 3 V to 3.6 V supply range suits a dedicated +3.3 V rail, while careful differential-impedance routing is needed to preserve LVDS signal integrity across a connector or cable.
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Digital Signage Controller
A digital signage controller can use the DS90C365AMT when its graphics engine produces 18-bit parallel pixel data but the external display uses four LVDS lanes. The transmitter performs the parallel-to-differential conversion and supports an 87.5 MHz pixel clock, making it appropriate for compact display-controller boards where a wide parallel bus would consume excessive connector pins. The design must ensure that the selected receiver recognizes the transmitted data format and that timing configuration matches the sign controller's pixel clock. With four differential outputs, the PCB also needs controlled trace geometry, suitable return paths, and a defined connector or cable interface. Supply decoupling should be placed close to the device because display links can transition rapidly during synchronization and video-data updates.
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Professional Video Monitor
The DS90C365AMT is applicable to a professional video monitor when the source controller provides LVCMOS or LVTTL display data and the panel expects a compatible four-lane LVDS stream. Its verified 1.785 Gbps aggregate rate and 87.5 MHz pixel-clock capability support serialized transfer of an 18-bit display payload while preserving a compact external interface. The transmitter alone does not negotiate video timing or drive a panel directly; a compatible receiver, cable, and display panel must complete the link. Engineers should confirm supported resolutions, blanking intervals, synchronization behavior, and configuration options against the manufacturer documentation. Differential pair length matching and uninterrupted ground references are especially important when the LVDS connection crosses a long internal cable or a board-to-board connector.
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Embedded Flat-Panel Display
Embedded equipment with an 18-bit display interface can use the DS90C365AMT to reduce a parallel bus to four LVDS outputs. This is useful where a display module uses a compact connector, where connector fanout would otherwise be high, or where a system board and display controller are separated by a short cable. The 48-TSSOP package supports conventional surface-mount assembly, and the specified 3 V to 3.6 V supply range allows operation from a regulated +3.3 V rail. Implementation should not assume that every LVDS panel is compatible: the receiver data format, clocking, lane mapping, and supported timing must be confirmed. The transmitter's serializer behavior and configuration settings should also be reviewed against the source controller to prevent unrecognized data formats even when the electrical layers are correctly connected.
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Medical Display Interface
A medical display interface can use the DS90C365AMT when the system controller supplies 18-bit LVCMOS/LVTTL data and the display module requires a compatible four-lane LVDS connection. The part's 87.5 MHz pixel-clock capability and 1.785 Gbps aggregate data rate make it a candidate for compact diagnostic or monitoring displays, provided the panel timing and receiver are supported. Because display clarity depends on reliable data transfer, the design must provide controlled LVDS impedance, solid grounding, and tested recovery behavior. Medical-device design teams must also evaluate applicable system-level qualification and risk controls separately from the component specifications. The verified data does not identify an AEC-Q100 or medical-specific qualification for this part, so neither standard should be inferred from its display-interface function.
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Test and Measurement Display
The DS90C365AMT can serve as the parallel-to-LVDS link in a test or measurement instrument that uses a compact high-resolution display. The 18-bit display format supports a substantial pixel payload, while four differential streams reduce the number of conductors required between the instrument's main board and display electronics. The verified 87.5 MHz link and 1.785 Gbps aggregate rate must be reconciled with the instrument's actual refresh rate, active display area, and blanking requirements. Because test equipment often contains switching converters and fast digital circuitry, the LVDS routing needs deliberate separation from noisy power paths and switching nodes. Power delivery to the transmitter should use a compact +3.3 V rail with local high-frequency decoupling, while the ground reference beneath the differential pairs should remain continuous.
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추천 제품 요약
엔지니어링 참조 데이터: DS90C365AMT — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DS90C363 | DS90C363A | DS90C365 | DS90C363B |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TSSOP | 48-TSSOP | 48-TSSOP | 48-TSSOP | 48-TSSOP |
| Product Type | Programmable LVDS flat-panel-display transmitter | LVDS flat-panel-display transmitter | LVDS flat-panel-display transmitter | LVDS flat-panel-display transmitter | Flat Panel Display Link transmitter |
| LVDS Output Channels | 4 differential data streams | 4 differential data streams | 4 differential data streams | 4 differential data streams | 4 differential data streams |
| Documented Pin Compatibility | DS90C365A replaces DS90C363, DS90C363A, and DS90C365 | Pin-to-pin compatible predecessor | Pin-to-pin compatible predecessor | Pin-to-pin compatible predecessor | Related family comparison verified |
주요 차별점
- Newer A-series feature set (vs DS90C363)
- Documented pin-compatible upgrade path (vs DS90C363A)
- Confirmed high-speed four-lane output (vs DS90C365)
설계 노트
Route each LVDS differential pair as a tightly coupled, length-matched pair with a continuous reference plane. The verified data confirms four LVDS outputs, but the supplied excerpts do not state the required trace impedance or maximum trace length. Derive those values from the complete DS90C365A datasheet and the selected receiver, then apply the same constraints through connectors and internal display cables.
Place local input, output, and bypass capacitors close to their associated device pins according to the manufacturer layout guidance. Keep the +3.3 V rail quiet because the verified operating range is only 3 V to 3.6 V. Avoid routing LVDS signals parallel to switching-node paths or high-current return paths, and provide a solid ground reference beneath each differential pair to limit radiated noise and susceptibility.
Do not treat pin-to-pin compatibility as proof that two display transmitters have identical behavior. Texas Instruments states that DS90C365A adds features and improvements relative to DS90C363, DS90C363A, and DS90C365. Before substitution, compare configuration registers, supported timing, receiver expectations, initialization sequence, and power behavior using the complete manufacturer documentation.
Keep the parallel LVCMOS/LVTTL source traces short where practical because their edge rates can produce crosstalk before serialization. Confirm the source-controller and transmitter voltage levels, organize the 21-bit input according to the documented mapping, and use test points that do not disrupt the differential pair geometry. A logic-state analyzer or dedicated interface analyzer can assist with validation, but it must support the applicable LVDS data format and clock rate.
규정 준수 정보
The supplied verified results do not explicitly state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status. Compliance must be confirmed from the current Texas Instruments product page or manufacturer declaration.
